Abstract: A method for fabricating a III-nitride semiconductor body that includes high temperature and low temperature growth steps.

Abstract: A method for fabricating a III-nitride semiconductor body that includes high temperature and low temperature growth steps.

Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.

Abstract: A method for fabricating a III-nitride semiconductor body that includes high temperature and low temperature growth steps.

Abstract: III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure may include a dielectric layer that is epitaxially grown using a III-nitride material to provide a simplified manufacturing process. The process permits the use of planar manufacturing technology to avoid additional manufacturing costs. High voltage power ICs have improved performance in a smaller package in comparison to corresponding silicon structures.

Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.

Abstract: A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.

Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.

Abstract: A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.

Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.

Abstract: A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.

Abstract: Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chemical etch. The desired isolation area may be identified by changing the conductivity type of the semiconductor material to be etched. The etch process can remove a conductive layer to isolate a device atop the conductive layer. The etch process can be self stopping, where the process automatically terminates when the selectively doped semiconductor material is removed.

Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.

Abstract: A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications.

Abstract: A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.

Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.

Abstract: A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.

Abstract: A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.

Abstract: A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.

Abstract: A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.