Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

Abstract: An efficient clock start and stop apparatus for clock forwarded system I/O. The apparatus may include a buffer coupled to receive incoming data from a data source. The buffer is clocked by a first clock signal that is provided by the data source. The buffer is configured to store the incoming data in a plurality of sequential lines in response to the first clock signal. The buffer may be further configured to store a plurality of bits in a plurality of occupied-bit registers. Each one of the plurality of occupied-bit registers indicates that data is present in a corresponding sequential line in the buffer. The apparatus may further include a clock gate circuit coupled to the buffer and configured to provide a second clock signal. The clock gate circuit may be further configured to start the second clock signal when valid data is present in the buffer and to stop the second clock signal when no data is present in the buffer.

Abstract: A method and apparatus for combined transaction reordering and buffer management. The apparatus may include a buffer, a first generator circuit and a second generator circuit. The buffer is configured to store memory transaction responses received from a memory controller in a plurality of addressable locations. The first generator circuit is configured to generate a first memory transaction request encoded with a first tag corresponding to an address in the buffer in response to receiving a first memory request. The second generator circuit is configured to generate a second tag using the size of said first memory request added to the first tag. The first generator circuit may be further configured to generate a second memory transaction request encoded with the second tag corresponding to a second address in the buffer in response to receiving a second memory request successive to the first memory request.