Abstract: The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.

Abstract: The present invention is a method and system for compensation of frequency pulling in an all digital phase lock loop. The all digital phase lock loop can utilize a multi-phase oscillator including latches with substantially all of the latches paired with a corresponding dummy cell. The dummy cells can have impedance characteristics, such as variable capacitance values which correspond to the variable capacitance value of the latches such that the sum of the two variable capacitance values remains substantially constant, even when the polarity of the reference clock signal changes. The dummy cells can be, for example, variable capacitors or dummy latches. The phase lock loop can also include a multiplying unit. The multiplying unit can receive a reference clock signal and generate a frequency multiplied reference clock signal.

Abstract: A transmitter generates first and second constant-envelope radio frequency (RF) component signals having first and second phase angles. The first and second phases are controlled by a phase controller. First and second nonlinear power amplifiers (PAs) are modulated by an amplitude-modulated power supply signal as the first and second constant-envelope RF component signals are amplified. The phase controller controls the first and second phases of the first and second constant-envelope RF component signals, in response to a power control signal, and, in so doing, controls an effective load impedance seen at the outputs of the first and second nonlinear PAs. By controlling the effective load impedance in response to a power control signal, rather than in response to rapid amplitude variations in an input signal envelope, the output power of the transmitter is efficiently controlled over a wide dynamic range even at low output powers.

Abstract: A broad power band transmitter utilizing a duty cycle modulator achieves 80dB of power range for 3G signals. The present invention greatly improves the efficiency of transmitters used in mobile phones, for example, by using the duty cycle modulator during medium and low power levels of the transmitting power amplifier. The power amplifier operates in three different modes based upon the amplifier power level selected. The power amplifier operates in an EER mode during high power levels, in a DCM ERR mode during medium power levels, and in a DCM mode during low power levels.

Abstract: The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.

Abstract: The present invention is a method and system for compensation of frequency pulling in an all digital phase lock loop. The all digital phase lock loop can utilize a multi-phase oscillator including latches with substantially all of the latches paired with a corresponding dummy cell. The dummy cells can have impedance characteristics, such as variable capacitance values which correspond to the variable capacitance value of the latches such that the sum of the two variable capacitance values remains substantially constant, even when the polarity of the reference clock signal changes. The dummy cells can be, for example, variable capacitors or dummy latches. The phase lock loop can also include a multiplying unit. The multiplying unit can receive a reference clock signal and generate a frequency multiplied reference clock signal.

Abstract: A connector system facilitates the connection of a first tree trunk to a second tree trunk of an artificial tree system, and further protects one or more ends of a trunk when, for example, the artificial tree system is being shipped or stored. The connector system comprises a sleeve. The sleeve comprises a cylindrical shaped body. The outer of the body has a uniform cylindrical shape. The interior of the sleeve has different diameters at its top and bottom. The interior includes a notch or shoulder. The shoulder is in proximity to the top end of the sleeve. The sleeve further comprises a cutout for assisting with connecting and securing the trunks together.

Abstract: Methods and apparatus for transmitting communications signals that are both power efficient and effective at avoiding or reducing transmitter-generated receive band noise. An exemplary transceiver apparatus includes a multi-mode transmitter that is configurable to operate in a plurality of operating modes (e.g., a polar mode, a quadrature mode and a hybrid mode), a receiver, and an operating mode controller. The operating mode controller is configured to control which operating mode the transmitter is to operate, depending on one or more of a transmit (Tx) power, receive (Rx) power, the Tx power relative to the Rx power, a level of frequency separation between a Tx frequency band and a Rx frequency band (Tx/Rx band separation), and modulation type employed by the transmitter.

Abstract: A multiple-mode modulator is configured similarly to a direct conversion quadrature modulator with an infusion of an amplitude modulation signal path from a large signal polar modulator to improve the power amplifier efficiency. The multiple-mode modulator also includes a radio frequency signal path. The multiple-mode modulator is configured to receive a baseband signal, convert the baseband signal to a radio frequency (RF) signal, and to process the RF signal according to either a polar mode or a quadrature mode, depending on a time-varying input voltage of the RF signal. When the power amplifier operates in the linear region, the RF signal is processed according to the quadrature mode. When the power amplifier operates in the compressed region, the RF signal is processed according to the polar mode. The multiple-mode modulator can be configured according to a small signal polar architecture or a large signal polar architecture, having either an open-loop or closed-loop configuration.

Abstract: The present invention is a lamp system for use in a light string system comprising a light assembly and a socket assembly. The light assembly comprises a light source, a base in communication with the light source, and a bypass activating system. The socket assembly comprises a socket adapted to receive the light assembly and a bypass mechanism having a first position and a second position. The bypass activating system is adapted to move the bypass mechanism between the first and second positions.

Abstract: A low cost high-efficiency all-digital transmitter using all-digital power amplifiers (“DPA”) and various mapping techniques to generate an output signal, which substantially reproduces a baseband signal at a carrier frequency. A baseband signal generator generates a baseband signal which is quantized by a signal processor using a quantization map. A DPA control mapper outputs control signals to phase selectors using the quantized signal and a quantization table. Each phase selector receives one of the control signals and outputs a waveform at a carrier frequency with a phase corresponding to the control signals, or an inactive signal. Each DPA in a DPA array has an assigned weight, receives one of the waveforms from the phase selectors, and outputs a power signal according to the weight of the DPA and the phase of the received waveform. The combined power signal substantially reproduces the baseband signal at the carrier frequency.

Abstract: A lamp system used in a light string system comprises a light assembly and a socket assembly. The light assembly comprises a light source, a base in communication with the light source, and a bypass activating system. The socket assembly comprises a socket adapted to receive the light assembly and a bypass mechanism having a first position and a second position. The bypass mechanism is in the first position when the light assembly is not seated in the socket assembly. When the bypass mechanism in the first position, current flows across the bypass mechanism. When the light assembly is inserted into the socket assembly, the bypass activating system of the light assembly moves the bypass mechanism into the second position, and current flows through the light source instead of the bypass mechanism.

Abstract: Envelope tracking (ET) methods and systems for controlling the delivery of power to radio frequency power amplifiers (RFPAs). An exemplary ET system includes an RFPA and a wide bandwidth capable and power efficient envelope modulator that includes a first power supplying apparatus and a second power supplying apparatus. The first power supplying apparatus includes a switch-mode converter and a regulator. The first mode converter is operable to dynamically step down a fixed power supply voltage according to amplitude variations in an envelope signal received by the regulator, and use the resulting dynamic power supply signal to power the regulator. The second power supplying apparatus is connected in parallel with the first power supplying apparatus. Depending on a power of an output signal to be generated at an output of the power amplifier, power is supplied to the power amplifier from either or both of the first and second power supplying apparatuses.

Abstract: The disclosure provides an effective means for fine-resolution determination of the frequency content of an RF signal using low speed digital circuits. The disclosure relates to a method and apparatus for decomposing a high frequency RF signal into several low frequency signals or data streams without loss of any information and without the use of extraneous circuit components such as local oscillators, mixers or offset phase-locked loops. Single or multiple phase oscillator outputs are fed directly to a single or multiple direct RF frequency-to-digital (DrfDC) circuits. The front end of the DrfDC circuit decomposes a high frequency signal into several low frequency signals without loss of any information. The low frequency signals are processed by the back-end of the DrfDC and converted into digital data streams. The digital data streams are then combined and averaged to represent the frequency of the input RF signal.

Abstract: A phase lock loop utilizes a multiphase oscillator having a plurality of digital inputs. A plurality of DQ flip-flops, offset in time from each other generate a plurality of control signals to remove control phase information from the oscillator in digital form. A DQ flip-flop connected between any two digital inputs on the oscillator determines direction of the traveling wave. The direction and phase information address a look-up table to determine the current fractional phase of the oscillator. A divide by N circuit is used to reduce the oscillator frequency. A total phase indicator signal for the oscillator is determined using the current fractional phase. The total phase is compared to a reference phase to produce a control signal for making adjustments to the oscillator. In a feed-forward path, frequency dividers divide a high frequency signal from the oscillator to a lower desired frequency, thereby increasing phase resolution.

Abstract: The disclosure relates to a method and apparatus for providing efficient signal transmission. Conventional linear amplifiers are most efficient when operated in compressed mode. In the compressed mode, the digital power amplifier switches between the on and off modes. A digital power amplifier operates in compressed mode only if the incoming signal is an on-off constant envelop signal. In one embodiment, the disclosure provides a method and apparatus for converting a digital baseband signal to on-off constant envelop signals for processing through binary-weighted or thermometer-weighted amplifier which are operated in compressed mode.

Abstract: A two-point modulator using a voltage control oscillator includes: a modulation section including a feedback circuit for performing feedback control of a signal outputted from the voltage control oscillator based on an inputted modulated signal, and a feedforward circuit for calibrating the modulated signal and outputting the calibrated modulated signal to the voltage control oscillator; a signal output section for, upon calibration processing, outputting a predetermined reference signal in place of the modulated signal, to the modulation section; and a gain correction section for, in a state where the feedback circuit is in an open loop state, calculating a frequency transition amount of the reference signal outputted from the voltage control oscillator, and correcting a gain used for calibration of the modulated signal performed by the feedforward circuit, based on the calculated frequency transition amount.

Abstract: A method of creating a design-specific I/O model document can include reading a plurality of I/O pin models corresponding to available I/O pin profiles on a target device (355) and identifying I/O pins of the target device that are used by a circuit design (325). An I/O pin profile for each I/O pin of the target device that is used by the circuit design can be determined (345). An I/O pin model can be selected from the plurality of I/O pin models for each I/O pin of the target device that is used by the circuit design according to the I/O pin profiles (355). The design-specific I/O model document for the circuit design can be generated by including each selected I/O pin model within the design-specific I/O model document (365). The design-specific I/O model document can be output (380).

Abstract: A broad power band transmitter utilizing a duty cycle modulator achieves 80dB of power range for 3G signals. The present invention greatly improves the efficiency of transmitters used in mobile phones, for example, by using the duty cycle modulator during medium and low power levels of the transmitting power amplifier. The power amplifier operates in three different modes based upon the amplifier power level selected. The power amplifier operates in an EER mode during high power levels, in a DCM ERR mode during medium power levels, and in a DCM mode during low power levels.

Abstract: The present invention is directed towards devices combining swimming pool skimmers, pumps, and removable, disposable filters into integral, sidewall-mounted systems for above-ground pools and other above-ground liquid containment enclosures, and methods for the use of such systems to remove both larger floating debris and smaller particulate matter to maintain water clarity and hygienic safety within such pools or like liquid containment enclosures. Specifically, the present invention is a ring-type above-ground pool comprising a base, a sidewall, and at least a portion of a cleaning system solely supported by the sidewall and mounted at a non-vertical angle such that it is substantially parallel to the sidewall.