Patents by Inventor Paul D. Agnello
Paul D. Agnello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8227792Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.Type: GrantFiled: February 14, 2008Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Paul D. Agnello, Stephen W. Bedell, Robert H. Dennard, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
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Patent number: 7683434Abstract: Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.Type: GrantFiled: August 13, 2008Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Paul D. Agnello, Rajeev Malik, K. Paul Muller
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Publication number: 20080303070Abstract: Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.Type: ApplicationFiled: August 13, 2008Publication date: December 11, 2008Inventors: Paul D. Agnello, Rajeev Malik, K. Paul Muller
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Patent number: 7459384Abstract: Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.Type: GrantFiled: June 28, 2004Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: Paul D. Agnello, Rajeev Malik, K. Paul Muller
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Publication number: 20080135875Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.Type: ApplicationFiled: February 14, 2008Publication date: June 12, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul D. Agnello, Stephen W. Bedell, Robert H. Dennard, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
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Patent number: 7361556Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.Type: GrantFiled: July 31, 2006Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: James W. Adkisson, Paul D. Agnello, Arne W. Ballantine, Rama Divakaruni, Erin C. Jones, Edward J. Nowak, Jed H. Rankin
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Patent number: 7358166Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.Type: GrantFiled: August 19, 2005Date of Patent: April 15, 2008Assignee: International Business Machines CorporationInventors: Paul D. Agnello, Stephen W. Bedell, Robert H. Dennard, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
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Patent number: 7265417Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.Type: GrantFiled: June 16, 2004Date of Patent: September 4, 2007Assignee: International Business Machines CorporationInventors: James W. Adkisson, Paul D. Agnello, Arne W. Ballantine, Rama Divakaruni, Erin C. Jones, Edward J. Nowak, Jed H. Rankin
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Patent number: 7163864Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.Type: GrantFiled: October 18, 2000Date of Patent: January 16, 2007Assignee: International Business Machines CorporationInventors: James W. Adkisson, Paul D. Agnello, Arne W. Ballantine, Rama Divakaruni, Erin C. Jones, Edward J. Nowak, Jed H. Rankin
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Patent number: 7112845Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.Type: GrantFiled: June 18, 2002Date of Patent: September 26, 2006Assignee: International Business Machines CorporationInventors: James W. Adkisson, Paul D. Agnello, Arne W. Ballantine, Rama Divakaruni, Erin C. Jones, Jed H. Rankin
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Patent number: 6946373Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.Type: GrantFiled: November 20, 2002Date of Patent: September 20, 2005Assignee: International Business Machines CorporationInventors: Paul D. Agnello, Stephen W. Bedell, Robert H. Dennard, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
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Patent number: 6916729Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.Type: GrantFiled: April 8, 2003Date of Patent: July 12, 2005Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Sunfei Fang, Keith Kwong Hon Wong, Paul D. Agnello, Christian Lavoie, Lawrence A. Clevenger, Chester T. Dziobkowski, Richard J. Murphy, Patrick W. DeHaven, Nivo Rovedo, Hsiang-Jen Huang
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Patent number: 6891228Abstract: A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.Type: GrantFiled: September 28, 2004Date of Patent: May 10, 2005Assignee: International Business Machines CorporationInventors: Heemyong Park, Byoung H. Lee, Paul D. Agnello, Dominic J. Schepis, Ghavam G. Shahidi
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Patent number: 6828630Abstract: A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.Type: GrantFiled: January 7, 2003Date of Patent: December 7, 2004Assignee: International Business Machines CorporationInventors: Heemyong Park, Byoung H. Lee, Paul D. Agnello, Dominic J. Schepis, Ghavam G. Shahidi
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Publication number: 20040203229Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.Type: ApplicationFiled: April 8, 2003Publication date: October 14, 2004Inventors: Sunfei Fang, Keith Kwong Hon Wong, Paul D. Agnello, Christian Lavoie, Lawrence A. Clevenger, Chester T. Dziobkowski, Richard J. Murphy, Patrick W. DeHaven, Nivo Rovedo, Hsiang-Jen Huang
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Publication number: 20040129979Abstract: A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.Type: ApplicationFiled: January 7, 2003Publication date: July 8, 2004Applicant: International Business Machines CorporationInventors: Heemyong Park, Byoung H. Lee, Paul D. Agnello, Dominic J. Schepis, Ghavam G. Shahidi
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Publication number: 20040094763Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul D. Agnello, Stephen W. Bedell, Robert H. Dennard, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
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Patent number: 6686617Abstract: A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.Type: GrantFiled: June 11, 2001Date of Patent: February 3, 2004Assignee: International Business Machines CorporationInventors: Paul D. Agnello, Bomy A. Chen, Scott W. Crowder, Ramachandra Divakaruni, Subramanian S. Iyer, Dennis Sinitsky
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Patent number: 6593660Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure including a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.Type: GrantFiled: May 29, 2001Date of Patent: July 15, 2003Assignee: International Business Machines CorporationInventors: Leena P. Buchwalter, Barbara Luther, Paul D. Agnello, John P. Hummel, Terence Lawrence Kane, Dirk Karl Manger, Paul Stephen McLaughlin, Anthony Kendall Stamper, Yun Yu Wang
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Patent number: 6563131Abstract: Off-current is not compromised in a field effect transistor having a gate length less than 100 nanometers in length by maintaining the conduction channel width one-half to one-quarter of the gate length and locating the gate on at least two sides of the conduction channel and to thus create a full depletion device. Such a narrow conduction channel is achieved by forming a trough at minimum lithographic dimensions, forming sidewalls within the trough and etching the gate structure self-aligned with the sidewalls. The conduction channel is then epitaxially grown from the source structure in the trough such that the source, conduction channel and drain region are a unitary monocrystalline structure.Type: GrantFiled: June 2, 2000Date of Patent: May 13, 2003Assignee: International Business Machines CorporationInventors: James W. Adkisson, Paul D. Agnello, Arne W. Ballantine, Christopher S. Putnam, Jed H. Rankin