Abstract: Formation of sidewalls on a gate structure in layers having a differential etch rate for certain etchants allows metallization and salicide formation annealing of a gate electrode and source/drain regions prior to shallow impurity implantation and impurity activation annealing at the location of a removable portion of a sidewall spacer establishing a gap between source/drain regions and remaining sidewalls of a gate structure. Therefore, diffusion of impurities to a greater depth and impurity deactivation during salacide formation annealing is avoided in a high performance semiconductor device such as a field effect transistor of extremely small dimensions.

Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

Abstract: An SOI circuit configuration effective for minimizing plasma-induced charging damage during fabrication comprises the formation of charge collectors connected to the gate electrode and the semiconductor body, wherein each one of the charge collectors have the same or substantially the same shape and dimension. A connecting structure formed between a device fabricated on SOI substrate and substrate is delayed until the latter stages of processing.

Abstract: A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spacer regions are formed on sides of the sidewall spacer regions. Upper regions of the gate structure and the sidewall spacer regions are silicided. Portions of source and drain extension regions in the semiconductor substrate adjacent the gate structure are also silicided.

Abstract: The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts.

Abstract: A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spacer regions are formed on sides of the sidewall spacer regions. Upper regions of the gate structure and the sidewall spacer regions are silicided. Portions of source and drain extension regions in the semiconductor substrate adjacent the gate structure are also silicided.

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure comprising a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

Abstract: A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

Abstract: A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

Abstract: A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spacer regions are formed on sides of the sidewall spacer regions. Upper regions of the gate structure and the sidewall spacer regions are silicided. Portions of source and drain extension regions in the semiconductor substrate adjacent the gate structure are also silicided.

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure comprising a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure.

Abstract: A method of maintaining an optimum pressure and purity level in a vessel having an inlet gas flow and an outlet gas flow during shutdown of the vessel that prevents imploding of the vessel when the inlet and outlet gas flows are discontinued. Gas from the vessel is directed to a containment portion in communication with the vessel. The pressure of the gas in the containment portion is monitored; the containment portion is backfilled with a purified inert gas when the monitored pressure drops to a predetermined lower level; and the containment portion is vented when the monitored pressure rises to a predetermined higher level. Apparatus for maintaining an optimum pressure and purity level in a vessel having an inlet gas flow and an outlet gas flow during shutdown of the vessel that prevents imploding of the vessel when the inlet and outlet gas flows are discontinued is also provided.

Abstract: A method and a device directed to the same, for stabilizing cobalt di-silicide/single crystal silicon, amorphous silicon, polycrystalline silicon, germanide/crystalline germanium, polycrystalline germanium structures or other semiconductor material structures so that high temperature processing steps (above 750.degree. C.) do not degrade the structural quality of the cobalt di-silicide/silicon structure. The steps of the method include forming a di-silicide or germanide by either reacting cobalt with the substrate material and/or the codeposition of the di-silicide or germanide on a substrate, adding a selective element, either platinum or nitrogen, into the cobalt and forming the di-silicide or germanide by a standard annealing treatment. Alternatively, the cobalt di-silicide or cobalt germanide can be formed after the formation of the di-silicide or germanide respectively. As a result, the upper limit of the annealing temperature at which the di-silicide or germanide will structurally degrade is increased.

Abstract: A method and a device directed to the same, for stabilizing cobalt silicide/single crystal silicon, amorphous silicon, polycrystalline silicon, germanide/crystalline germanium, polycrystalline germanium structures or other semiconductor material structures so that high temperature processing steps (above 750.degree. C.) do not degrade the structural quality of the cobalt silicide/silicon structure. The steps of the method include forming a silicide or germanide by either reacting cobalt with the substrate material and/or the codeposition of the silicide or germanide on a substrate, adding a selective element, either platinum or nitrogen, into the cobalt and forming the silicide germanide by a standard annealing treatment. Alternatively, the cobalt silicide or cobalt germanide can be formed after the formation of the silicide or germanide respectively. As a result, the upper limit of the annealing temperature at which the silicide or germanide will structurally degrade is increased.

Abstract: A multilayer structure having an oxygen or dopant diffusion barrier fabricated of an electrically conductive, thermally stable material of refractory metal-silicon-nitrogen which is resistant to oxidation, prevents out-diffusion of dopants from silicon and has a wide process window wherein the refractory metal is selected from Ta, W, Nb, V, Ti, Zr, Hf, Cr and Mo.

Abstract: A method of maintaining an optimum pressure and purity level in a vessel having an inlet gas flow and an outlet gas flow during shutdown of the vessel that prevents imploding of the vessel when the inlet and outlet gas flows are discontinued. Gas from the vessel is directed to a containment portion in communication with the vessel. The pressure of the gas in the containment portion is monitored; the containment portion is backfilled with a purified inert gas when the monitored pressure drops to a predetermined lower level; and the containment portion is vented when the monitored pressure rises to a predetermined higher level. Apparatus for maintaining an optimum pressure and purity level in a vessel having an inlet gas flow and an outlet gas flow during shutdown of the vessel that prevents imploding of the vessel when the inlet and outlet gas flows are discontinued is also provided.

Abstract: A system and method for growing low defect density epitaxial layers of Si on imperfectly cleaned Si surfaces by either selective or blanket deposition at low temperatures using the APCVD process wherein a first thin, e.g., 10 nm, layer of Si is grown on the surface from silane or disilane, followed by the growing of the remainder of the film from dichlorosilane (DCS) at the same low temperature, e.g., 550.degree. C. to 850.degree. C. The subsequent growth of the second layer with DCS over the first layer, especially if carried out immediately in the very same deposition system, will not introduce additional defects and may be coupled with high and controlled n-type doping which is not available in a silane-based system.

Abstract: A system and method for growing low defect density epitaxial layers of Si on imperfectly cleaned Si surfaces by either selective or blanket deposition at low temperatures using the APCVD process wherein a first thin, e.g., 10 nm, layer of Si is grown on the surface from silane or disilane, followed by the growing of the remainder of the film from dichlorosilane (DCS) at the same low temperature, e.g., 550.degree. C. to 850.degree. C. The subsequent growth of the second layer with DCS over the first layer, especially if carried out immediately in the very same deposition system, will not introduce additional defects and may be coupled with high and controlled n-type doping which is not available in a silane-based system.