Patents by Inventor Paul D. Brabant

Paul D. Brabant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170194138
    Abstract: A selective semiconductor deposition process that employs an alternating sequence of a deposition step and an etch step. During each deposition step, a semiconductor material is deposited on single crystalline surfaces at a greater deposition rate than on insulator surfaces. A combination of hydrogen chloride and a germanium-containing gas is employed within each etch step. The germanium-containing gas is employed to enhance the etch rate of hydrogen chloride, thereby enabling an effective etch process at temperatures as low as 380° C. Deposited semiconductor material is removed from above insulator surfaces, while a fraction of the deposited semiconductor material remains on semiconductor surfaces after each etch step, thereby providing a selective deposition of the semiconductor material.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Paul D. Brabant, Keith Chung, Hong He, Devendra K. Sadana, Manabu Shinriki, Yunpeng Yin, Zhengmao Zhu
  • Patent number: 9218962
    Abstract: A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium precursor gas is employed to deposit an epitaxial semiconductor alloy material including at least silicon and germanium on a single crystalline surface. The germanium precursor gas effectively reduces the gas phase reaction of the high order silane, thereby improving the thickness uniformity of the deposited epitaxial semiconductor alloy material. The combination of the high order silane and the germanium precursor gas provides a high deposition rate in the Frank-van der Merwe growth mode for deposition of a single crystalline semiconductor alloy material.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: December 22, 2015
    Assignees: GLOBALFOUNDRIES INC., MATHESON TRI-GAS, INC.
    Inventors: Paul D. Brabant, Keith Chung, Hong He, Devendra K. Sadana, Manabu Shinriki
  • Publication number: 20140045324
    Abstract: A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium precursor gas is employed to deposit an epitaxial semiconductor alloy material including at least silicon and germanium on a single crystalline surface. The germanium precursor gas effectively reduces the gas phase reaction of the high order silane, thereby improving the thickness uniformity of the deposited epitaxial semiconductor alloy material. The combination of the high order silane and the germanium precursor gas provides a high deposition rate in the Frank-van der Merwe growth mode for deposition of a single crystalline semiconductor alloy material.
    Type: Application
    Filed: October 18, 2013
    Publication date: February 13, 2014
    Applicants: MATHESON TRI-GAS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul D. Brabant, Keith Chung, Hong He, Devendra K. Sadana, Manabu Shinriki
  • Patent number: 8642454
    Abstract: Cyclic deposit and etch (CDE) selective epitaxial growth employs an etch chemistry employing a combination of hydrogen chloride and a germanium-containing gas to provide selective deposition of a silicon germanium alloy at temperatures lower than 625° C. High strain epitaxial silicon germanium alloys having a germanium concentration greater than 35 atomic percent in a temperature range between 400° C. and 550° C. A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium-containing precursor gas is employed to deposit the silicon germanium alloy with thickness uniformity and at a high deposition rate during each deposition step in this temperature range. Presence of the germanium-containing gas in the etch chemistry enhances the etch rate of the deposited silicon germanium alloy material during the etch step.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: February 4, 2014
    Assignees: International Business Machines Corporation, Matheson Tri-Gas, Inc.
    Inventors: Paul D. Brabant, Keith Chung, Hong He, Devendra K. Sadana, Manabu Shinriki
  • Patent number: 8530340
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: September 10, 2013
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joseph P. Italiano, Chantal J. Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
  • Publication number: 20130040440
    Abstract: A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.
    Type: Application
    Filed: September 13, 2012
    Publication date: February 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Hong He, Alexander Reznicek, Devendra K. Sadana, Paul D. Brabant, Keith Chung, Manabu Shinriki
  • Publication number: 20130040438
    Abstract: A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.
    Type: Application
    Filed: August 9, 2011
    Publication date: February 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Hong He, Alexander Reznicek, Devendra K. Sadana, Paul D. Brabant, Keith Chung, Manabu Shinriki
  • Publication number: 20120295421
    Abstract: Cyclic deposit and etch (CDE) selective epitaxial growth employs an etch chemistry employing a combination of hydrogen chloride and a germanium-containing gas to provide selective deposition of a silicon germanium alloy at temperatures lower than 625° C. High strain epitaxial silicon germanium alloys having a germanium concentration greater than 35 atomic percent in a temperature range between 400° C. and 550° C. A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium-containing precursor gas is employed to deposit the silicon germanium alloy with thickness uniformity and at a high deposition rate during each deposition step in this temperature range. Presence of the germanium-containing gas in the etch chemistry enhances the etch rate of the deposited silicon germanium alloy material during the etch step.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul D. Brabant, Keith Chung, Hong He, Devendra K. Sadana, Manabu Shinriki
  • Patent number: 7901968
    Abstract: Some embodiments of the invention are related to manufacturing semiconductors. Methods and apparatuses are disclosed that provide thin and fully relaxed SiGe layers. In some embodiments, the presence of oxygen between a single crystal structure and a SiGe heteroepitaxial layer, and/or within the SiGe heteroepitaxial layer, allow the SiGe layer to be thin and fully relaxed. In some embodiments, a strained layer of Si can be deposited over the fully relaxed SiGe layer.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: March 8, 2011
    Assignee: ASM America, Inc.
    Inventors: Keith Doran Weeks, Paul D. Brabant
  • Patent number: 7837795
    Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: November 23, 2010
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joe P. Italiano, Jianqing Wen
  • Patent number: 7682947
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: March 23, 2010
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joseph P. Italiano, Chantal J. Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
  • Publication number: 20100006024
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Application
    Filed: September 9, 2009
    Publication date: January 14, 2010
    Applicant: ASM AMERICA, INC.
    Inventors: Paul D. Brabant, Joseph P. Italiano, Chantal J. Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
  • Patent number: 7462239
    Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 9, 2008
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joe P. Italiano, Jianqing Wen
  • Patent number: 7402504
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: July 22, 2008
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joseph P. Italiano, Chantal J. Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
  • Patent number: 7238595
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: July 3, 2007
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joseph P. Italiano, Chantal J. Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
  • Patent number: 7115521
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: October 3, 2006
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joseph P. Italiano, Chantal J. Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
  • Patent number: 7108748
    Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: September 19, 2006
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joe P. Italiano, Jianqing Wen
  • Patent number: 7029995
    Abstract: Methods for forming epitaxial films involve forming a buffer layer on a single crystal substrate, depositing an amorphous layer on the buffer layer, then forming an epitaxial film from the amorphous layer by solid phase epitaxy.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: April 18, 2006
    Assignee: ASM America, Inc.
    Inventors: Michael A. Todd, Paul D. Brabant, Keith D. Weeks, Jianqing Wen
  • Patent number: 6998305
    Abstract: A method of forming an electronic component having elevated active areas is disclosed. The method comprises providing a semiconductor substrate in a processing chamber. The semiconductor substrate has disposed thereon a polycrystalline silicon gate and exposed active areas. The method further comprises performing a deposition process in which a silicon-source gas is supplied into the processing chamber to cause polycrystalline growth on the gate and epitaxial deposition on the active areas. The method further comprises performing a flash etch back process in which polycrystalline material is etched from the gate at a first etching rate and the epitaxial layer is etched from the active areas at a second etching rate. The first etching rate is faster than the second etching rate. The deposition process and the flash etch back process can be repeated cyclically, if desired.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: February 14, 2006
    Assignee: ASM America, Inc.
    Inventors: Chantal J. Arena, Joe P. Italiano, Paul D. Brabant
  • Publication number: 20040219735
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Application
    Filed: March 12, 2004
    Publication date: November 4, 2004
    Inventors: Paul D. Brabant, Joseph P. Italiano, Chantal J. Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer