Abstract: A method of forming an electronic component having elevated active areas is disclosed. The method comprises providing a semiconductor substrate in a processing chamber. The semiconductor substrate has disposed thereon a polycrystalline silicon gate and exposed active areas. The method further comprises performing a deposition process in which a silicon-source gas is supplied into the processing chamber to cause polycrystalline growth on the gate and epitaxial deposition on the active areas. The method further comprises performing a flash etch back process in which polycrystalline material is etched from the gate at a first etching rate and the epitaxial layer is etched from the active areas at a second etching rate. The first etching rate is faster than the second etching rate. The deposition process and the flash etch back process can be repeated cyclically, if desired.

Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.