Abstract: A circuit is provided to facilitate temporal redundancy for inter-chip communication. When an inter-chip communication channel fails, data bits associated with the faulty channel are steered to a non-faulty channel and transmitted via the non-faulty channel together with data bits associated with the non-faulty channel at an increased data rate.

Abstract: An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first timing signal according to a test parameter. The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input.

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.

Abstract: Millimeter scale three dimensional antenna structures and methods for fabricating such structures are disclosed. According to one method, a first substantially planar die having a first antenna structure is placed on a first surface. A second substantially planar die having at least one conductive element is placed on a second surface that forms an oblique angle with the first surface. The first and second dies are mechanically coupled to each other such that the first die and the first antenna structure extend at the oblique angle to the second die.

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.

Abstract: Electrical connector parts for combining power delivery and signaling in inductively coupled connectors are disclosed. According to one aspect, an electrical connector part includes a first mating connector face having disposed thereon a first set of inductors and also includes a mechanical interface that is configured to maintain the first mating connector face in closely spaced apart relation to a second mating conductor face having disposed thereon a second set of inductors. The mechanical interface is designed to prevent DC coupling and provide inductive AC coupling between at least one pair of inductors made up of one inductor from the first set of inductors and one inductor from the second set of inductors. The first set of inductors includes a power inductor of a first size for transferring power and a data inductor of a second size different from the first size for transferring data.

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.

Abstract: AC powered logic circuits and systems including same are disclosed. According to one aspect, a system including a logic circuit powered using an alternating current (AC) power source includes at least one supply transistor connected to receive voltages of opposite phases from an AC power source such that the at least one supply transistor is strongly on during a first phase of the voltage of the AC power source and is strongly off during a second phase opposite the first phase of the voltage of the AC power source and at least one logic circuit connected to be powered by the AC power source through the at least one supply transistor and producing an output at an output terminal responsive to an input received at an input terminal.

Abstract: Methods, systems, and computer readable media for asymmetric multimode interconnect (MMI) are disclosed. According to one aspect, a system for receiver-side asymmetric MMI includes a receiver that receives binary-encoded input signals from a multichannel interconnect, encodes the received binary-encoded signals according to a multimode encoding equation to produce multimode-encoded signals having voltage levels according to the multimode encoding equation, adjusts the timing of the multimode-encoded signals to compensate for multichannel interconnect channel delays to produce delay-adjusted multimode-encoded signals, and decodes the delay-adjusted multimode-encoded signals according to a multimode decoding equation to produce binary-encoded output signals.

Abstract: A circuit is provided to facilitate temporal redundancy for inter-chip communication. When an inter-chip communication channel fails, data bits associated with the faulty channel are steered to a non-faulty channel and transmitted via the non-faulty channel together with data bits associated with the non-faulty channel at an increased data rate.

Abstract: Methods, systems, and computer readable media for low power multimode interconnect for lossy and tightly coupled multi-channel are disclosed. According to one aspect, a system for low power multimode interconnect includes a receiver for receiving a plurality of input signals that have been encoded by a multimode encoding equation to have voltage levels according to the multimode encoding equation and for decoding the received signals according to a multimode decoding equation to produce binary data as output, wherein the receiver includes a set of frequency-compensated amplifiers for emphasizing high-frequency components of the received input signals and a set of latches for receiving amplified signals from the frequency-compensated amplifiers and for decoding the amplified signals according to the multimode decoding equation to produce binary data as output.

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path.

Abstract: Methods, systems, and computer readable media for asymmetric multimode interconnect (MMI) are disclosed. According to one aspect, a system for receiver-side asymmetric MMI includes a receiver that receives binary-encoded input signals from a multichannel interconnect, encodes the received binary-encoded signals according to a multimode encoding equation to produce multimode-encoded signals having voltage levels according to the multimode encoding equation, adjusts the timing of the multimode-encoded signals to compensate for multichannel interconnect channel delays to produce delay-adjusted multimode-encoded signals, and decodes the delay-adjusted multimode-encoded signals according to a multimode decoding equation to produce binary-encoded output signals.

Abstract: Millimeter scale three dimensional antenna structures and methods for fabricating such structures are disclosed. According to one method, a first substantially planar die having a first antenna structure is placed on a first surface. A second substantially planar die having at least one conductive element is placed on a second surface that forms an oblique angle with the first surface. The first and second dies are mechanically coupled to each other such that the first die and the first antenna structure extend at the oblique angle to the second die.

Abstract: An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first timing signal according to a test parameter. The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input.

Abstract: Methods, systems, and computer readable media for low power multimode interconnect for lossy and tightly coupled multi-channel are disclosed. According to one aspect, a system for low power multimode interconnect includes a receiver for receiving a plurality of input signals that have been encoded by a multimode encoding equation to have voltage levels according to the multimode encoding equation and for decoding the received signals according to a multimode decoding equation to produce binary data as output, wherein the receiver includes a set of frequency-compensated amplifiers for emphasizing high-frequency components of the received input signals and a set of latches for receiving amplified signals from the frequency-compensated amplifiers and for decoding the amplified signals according to the multimode decoding equation to produce binary data as output.

Abstract: AC powered logic circuits and systems including same are disclosed. According to one aspect, a system including a logic circuit powered using an alternating current (AC) power source includes at least one supply transistor connected to receive voltages of opposite phases from an AC power source such that the at least one supply transistor is strongly on during a first phase of the voltage of the AC power source and is strongly off during a second phase opposite the first phase of the voltage of the AC power source and at least one logic circuit connected to be powered by the AC power source through the at least one supply transistor and producing an output at an output terminal responsive to an input received at an input terminal.

Abstract: Multilayer floating gate field-effect transistor (FET) devices and related methods are provided. A multilayer floating gate FET device can include a first floating gate separated via a first dielectric layer from a channel of the device and a second floating gate separated via a second dielectric layer from the first floating gate. The second dielectric layer between the first floating gate and the second floating gate permits a redistribution of charge between the first and second floating gates from one of the floating gates to the other when under the influence of a first electrical field from a first voltage. In some embodiments, a redistribution of charge between the first and second floating gates with electrons being supplied through a channel to the first and second floating gates can occur when under the influence of a second electrical field from a second voltage that is greater than the first voltage.

Abstract: Systems, methods, and computer readable media for fractional pre-emphasis of multi-mode interconnect are disclosed. According to one aspect, the subject matter described herein includes a method for fractional pre-emphasis of multi-mode interconnect. Multiple bits of binary data are periodically received. For each period, the multiple bits of binary data are encoded into multiple scalar values, each value representing a level of an analog signal to be output over a multi-mode interconnect system during the current period. Multiple analog signal outputs are generated corresponding to multiple scalar values, each signal output being driven to a level according to its corresponding scalar value. For each representative scalar value, a difference between the scalar value generated during the current period and the scalar value generated during the previous period is determined, and a pre-emphasis signal that is proportional to the difference is generated.