Abstract: Systems, methods, and computer readable media for fractional pre-emphasis of multi-mode interconnect are disclosed. According to one aspect, the subject matter described herein includes a method for fractional pre-emphasis of multi-mode interconnect. Multiple bits of binary data are periodically received. For each period, the multiple bits of binary data are encoded into multiple scalar values, each value representing a level of an analog signal to be output over a multi-mode interconnect system during the current period. Multiple analog signal outputs are generated corresponding to multiple scalar values, each signal output being driven to a level according to its corresponding scalar value. For each representative scalar value, a difference between the scalar value generated during the current period and the scalar value generated during the previous period is determined, and a pre-emphasis signal that is proportional to the difference is generated.

Abstract: Methods and systems for fast packet forwarding include traversing a trie data structure stored in on-chip memory based on bits in an input address. The bits in the input address result in a predetermined location in the data structure. The number of bits that have a first value and that are located before the determined location is calculated. The calculated number of bits corresponds to an offset in a second memory device of an address to which the packet having the input address is to be forwarded. The address can be extracted using a single access to an off-chip memory device.

Abstract: Methods and systems for using binary searches for variable length network address prefix lookups are disclosed. Variable length prefixes are stored in a network address forwarding table. Each prefix corresponds to an entry in the forwarding table. The entries correspond to nodes in a binary tree. Each entry in the forwarding table includes path information regarding parent nodes of each entry in the binary tree. When a lookup is performed in the routing table, bits in the path information are used to determine the longest parent node prefix that matches the address being searched. The longest parent node prefix corresponds to the longest matching prefix.

Abstract: Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and/or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and/or first and second combined inductive and capacitive elements.

Abstract: Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and/or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and/or first and second combined inductive and capacitive elements.

Abstract: Methods and systems for using binary searches for variable length network address prefix lookups are disclosed. Variable length prefixes are stored in a network address forwarding table. Each prefix corresponds to an entry in the forwarding table. The entries correspond to nodes in a binary tree. Each entry in the forwarding table includes path information regarding parent nodes of each entry in the binary tree. When a lookup is performed in the routing table, bits in the path information are used to determine the longest parent node prefix that matches the address being searched. The longest parent node prefix corresponds to the longest matching prefix.

Abstract: Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and/or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and/or first and second combined inductive and capacitive elements.

Abstract: Methods and systems for fast packet forwarding include traversing a trie data structure stored in on-chip memory based on bits in an input address. The bits in the input address result in a predetermined location in the data structure. The number of bits that have a first value and that are located before the determined location is calculated. The calculated number of bits corresponds to an offset in a second memory device of an address to which the packet having the input address is to be forwarded. The address can be extracted using a single access to an off-chip memory device.