Patents by Inventor Paul D. Ruby
Paul D. Ruby has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10770128Abstract: A refreshing method is described. The method includes recognizing a set of blocks of a non-volatile memory for refreshing and then refreshing a subset of the data within the blocks, where, invalid data within the blocks is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.Type: GrantFiled: September 28, 2018Date of Patent: September 8, 2020Assignee: Intel CorporationInventors: Mark Anthony Golez, David J. Pelster, Xin Guo, Paul D. Ruby
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Patent number: 10289597Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: GrantFiled: May 9, 2018Date of Patent: May 14, 2019Assignee: Micron Technology, Inc.Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Publication number: 20190043556Abstract: A refreshing method is described. The method includes recognizing a set of blocks of a non-volatile memory for refreshing and then refreshing a subset of the data within the blocks, where, invalid data within the blocks is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.Type: ApplicationFiled: September 28, 2018Publication date: February 7, 2019Inventors: Mark Anthony GOLEZ, David J. PELSTER, Xin GUO, Paul D. RUBY
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Patent number: 10153015Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.Type: GrantFiled: September 13, 2017Date of Patent: December 11, 2018Assignee: Intel CorporationInventors: Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran
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Publication number: 20180329854Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: ApplicationFiled: May 9, 2018Publication date: November 15, 2018Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Patent number: 9996496Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: GrantFiled: August 24, 2017Date of Patent: June 12, 2018Assignee: Micron Technology, Inc.Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Publication number: 20180068695Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.Type: ApplicationFiled: September 13, 2017Publication date: March 8, 2018Inventors: Prashant S. DAMLE, Frank T. HADY, Paul D. RUBY, Kiran PANGAL, Sowmiya JAYACHANDRAN
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Publication number: 20170351637Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: ApplicationFiled: August 24, 2017Publication date: December 7, 2017Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Patent number: 9792963Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.Type: GrantFiled: November 11, 2015Date of Patent: October 17, 2017Assignee: Intel CorporationInventors: Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran
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Patent number: 9785603Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: GrantFiled: July 18, 2016Date of Patent: October 10, 2017Assignee: Micron Technology, Inc.Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Patent number: 9740437Abstract: Methods and apparatus related to a mechanism for quickly adapting garbage collection resource allocation for an incoming I/O (Input/Output) workload are described. In one embodiment, non-volatile memory stores data corresponding to a first workload and a second workload. Allocation of one or more resources in the non-volatile memory is determined based at least in part on a determination of an average validity of one or more blocks, where the one or more candidate bands are to be processed during operation of the first workload or the second workload. Other embodiments are also disclosed and claimed.Type: GrantFiled: March 27, 2015Date of Patent: August 22, 2017Assignee: Intel CorporationInventors: Neal R. Mielke, Mark Anthony Golez, David J. Pelster, Paul D. Ruby, Xin Guo
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Patent number: 9679658Abstract: Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.Type: GrantFiled: June 26, 2015Date of Patent: June 13, 2017Assignee: INTEL CORPORATIONInventors: David J. Pelster, Yogesh B. Wakchaure, Xin Guo, Paul D. Ruby, Justin R. Dayacap, Joseph F. Doller, Robert E. Frickey
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Patent number: 9558831Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.Type: GrantFiled: May 18, 2015Date of Patent: January 31, 2017Assignee: Micron Technology, Inc.Inventors: Paul D. Ruby, Violante Moschiano, Giovanni Santin
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Publication number: 20160379715Abstract: Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.Type: ApplicationFiled: June 26, 2015Publication date: December 29, 2016Inventors: David J. PELSTER, Yogesh B. WAKCHAURE, Xin GUO, Paul D. RUBY, Justin R. DAYACAP, Joseph F. DOLLER, Robert E. FRICKEY
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Publication number: 20160328353Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: ApplicationFiled: July 18, 2016Publication date: November 10, 2016Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Patent number: 9477616Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: GrantFiled: August 7, 2013Date of Patent: October 25, 2016Assignee: Micron Technology, Inc.Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Publication number: 20160283161Abstract: Methods and apparatus related to a mechanism for quickly adapting garbage collection resource allocation for an incoming I/O (Input/Output) workload are described. In one embodiment, non-volatile memory stores data corresponding to a first workload and a second workload. Allocation of one or more resources in the non-volatile memory is determined based at least in part on a determination of an average validity of one or more blocks, where the one or more candidate bands are to be processed during operation of the first workload or the second workload. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: March 27, 2015Publication date: September 29, 2016Applicant: Intel CorporationInventors: Neal R. Mielke, Mark Anthony Golez, David J. Pelster, Paul D. Ruby, Xin Guo
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Publication number: 20160189757Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.Type: ApplicationFiled: November 11, 2015Publication date: June 30, 2016Inventors: PRASHANT S. DAMLE, FRANK T. HADY, PAUL D. RUBY, KIRAN PANGAL, SOWMIYA JAYACHANDRAN
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Patent number: 9263130Abstract: Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time.Type: GrantFiled: July 7, 2014Date of Patent: February 16, 2016Assignee: Micron Technology, Inc.Inventors: Paul D. Ruby, Violante Moschiano
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Patent number: 9202547Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.Type: GrantFiled: March 15, 2013Date of Patent: December 1, 2015Assignee: Intel CorporationInventors: Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran