Abstract: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit lines pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated

Abstract: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated

Abstract: A circuit is provided for equalizing a signal between a pair of data lines. The circuit comprises a fist equalizing element that is operatively coupled between the pair of data lines for equalizing the signal, the first equalizing element being located proximate a first end of the pair of data lines. The circuit further comprises a precharging element that is operatively coupled between the pair of data lines for precharging the pair of data lines to a precharge voltage, the precharging element being located proximate to the first equalizing element. The circuit also comprises a second equalizing element that is operatively coupled between the pair of data lines for equalizing the signal, and located at a predetermined position along the data lines. As a result of having multiple equalizing elements located along pairs of bit lines, the precharge and equalize function is performed faster than in conventional approaches.

Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

Abstract: A circuit is provided for equalizing a signal between a pair of bit lines. The circuit comprises a first equalizing element that is operatively coupled between the pair of bit lines for equalizing the signal, the first equalizing element being located proximate a first end of the pair of bit lines. The circuit further comprises a precharging element that is operatively coupled between the pair of bit lines for precharging the pair of bit lines to a precharge voltage, the precharging element being located proximate to the first equalizing element. The circuit also comprises a second equalizing element that is operatively coupled between the pair of bit lines for equalizing the signal, and located at a predetermined position along the bit lines. As a result of having multiple equalizing elements located along pairs of bit lines, the precharge and equalize function is performed faster than in conventional approaches.

Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

Abstract: There is provided a latched comparison circuit for generating complementary latched output signals. The latched comparison circuit includes a comparator circuit for comparing an input address with a redundant address for generating a comparison output signal. The latched comparison circuit further includes a flip-flop circuit coupled to the comparison output signal for latching the comparison output signal and for providing complementary latched comparison output signals in response to a clock signal.

Abstract: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit lines pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated

Abstract: A differential data sensing and capture circuit, includes a differential input stage circuit for receiving respective ones of said differential data signals and having first and second output nodes. A latch element is provided, having first and second complementary inputs coupled to receive signals from said respective first and second output nodes. A gating circuit dynamically enables and disables a clock signal to the differential input stage in response to an enable signal, such that power consumption in said differential input stage is conserved. In a further embodiment the enable signal is a complementary clock input signal.

Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

Abstract: There is provided a latched comparison circuit for generating complementary latched output signals. The latched comparison circuit comprises a comparator circuit for comparing an input address with a redundant address for generating a comparison output signal. The latched comparison circuit further comprises a flip-flop circuit coupled to the comparison output signal for latching the comparison output signal and for providing complementary latched comparison output signals in response to a clock signal.

Abstract: A circuit is provided for equalizing a signal between a pair of bit lines. The circuit comprises a first equalizing element that is operatively coupled between the pair of bit lines for equalizing the signal, the first equalizing element being located proximate a first end of the pair of bit lines. The circuit further comprises a precharging element that is operatively coupled between the pair of bit lines for precharging the pair of bit lines to a precharge voltage, the precharging element being located proximate to the first equalizing element. The circuit also comprises a second equalizing element that is operatively coupled between the pair of bit lines for equalizing the signal, and located at a predetermined position along the bit lines. As a result of having multiple equalizing elements located along pairs of bit lines, the precharge and equalize function is performed faster than in conventional approaches.

Abstract: A circuit selectively adjusts the width of an input pulse. The circuit comprises two stages. The first stage delays a leading edge of the input pulse with respect to a trailing edge of the input pulse in accordance with a first control input. The second stage delays the trailing edge of the input pulse with respect to the leading edge of the input pulse in accordance with a second control input. The input pulse width is adjusted in accordance with a difference between the delay of the leading edge and the delay of the trailing edge.

Abstract: A delay locked loop based clocking circuit includes a lead delay line followed by a period delay line. The lead delay line receives an input clock signal and includes an analog delay control input. The period delay line has a plurality of taps and an analog delay control input, and is operated such that the N taps divide a single period of an input clock. A selected tap of the period delay line, sometimes called a “virtual zero-degree tap,” is fed back and phase-compared with the input clock signal to adjust the delay of the lead delay line.