Abstract: A flag and a wait period are used to guarantee that readers of two data values see the updated first value before they see the updated second value, where the second value has to be updated after the first value is updated and thus is dependent on the first value. The first value is updated, and a flag associated with the first data value is set. The flag effectively prevents further updating of the first data value until it has been cleared. A length of time is waited for, such that any reading of the first data value and the second data value is guaranteed to not see the second data value as updated unless the first data value is also seen as updated. The flag is then cleared, such that further updating of the first data value can again occur. The second data value is finally updated.

Abstract: Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Memory write operations local to a CPU are allowed to occur in an arbitrary order, and constraints are placed on shared memory operations. Multiple sets of instructions are provided in which order of execution of the instructions is maintained through the use of CPU registers, write buffers in conjunction with assignment of sequence numbers to the instruction, or a hierarchical ordering system. The system ensures that an earlier designated instruction has reach a specified state of execution prior to a latter instruction reaching a specified state of execution. The ordering of operations allows memory operations local to a CPU to occur in conjunction with other memory operations that are not affected by such execution.

Abstract: A flag and a wait period are used to guarantee that readers of two data values see the updated first value before they see the updated second value, where the second value has to be updated after the first value is updated and thus is dependent on the first value. The first value is updated, and a flag associated with the first data value is set. The flag effectively prevents further updating of the first data value until it has been cleared. A length of time is waited for, such that any reading of the first data value and the second data value is guaranteed to not see the second data value as updated unless the first data value is also seen as updated. The flag is then cleared, such that further updating of the first data value can again occur. The second data value is finally updated.

Abstract: Read-copy-update (RCU) is performed within real-time and other types of systems, such that memory barrier usage within RCU is reduced. A computerized system includes processors, memory, updaters, and readers. The updaters update contents of a section of the memory by using first and second sets of per-processor counters, first and second sets of per-processor need-memory-barrier bits, and a global flip-counter bit. The global flip-counter bit specifies which of the first or second set of the per-processor counters and the per-processor need-memory-barrier bits is a current set, and which is a last set. The readers read the contents of the section of the memory by using the first and second sets of per-processor counters, the first and second sets of per-processor need-memory-barrier bits, and the global flip-counter bit, in a way that eliminates the need for memory barriers during such read operations.

Abstract: A method, system and computer program product for modifying data elements in a shared data element group that must be updated atomically for the benefit of readers requiring group integrity. A global generation number is associated with the data element group and each member receives a copy of this number when it is created. Each time an update is performed, the global generation number is incremented and the updated element's copy of this number is set to the same value. For each updated data element, a link is maintained from the new version to the pre-update version thereof, either directly or using pointer-forwarding entities. When a search is initiated, the current global generation number is referenced at the commencement of the search. As data elements in the group are traversed, the reader traverses the links between new and old data element versions to find a version having a matching generation number, if any.

Abstract: A system, method and computer program product for efficient sharing of memory between first and second applications running under first and second operating systems on a shared hardware system. The hardware system runs a hypervisor that supports concurrent execution of the first and second operating systems, and further includes a region of shared memory managed on behalf of the first and second applications. Techniques are used to avoid preemption when the first application is accessing the shared memory region. In this way, the second application will not be unduly delayed when attempting to access the shared memory region due to delays stemming from the first application's access of the shared memory region. This is especially advantageous when the second application and operating system are adapted for real-time processing. Additional benefits can be obtained by taking steps to minimize memory access faults.

Abstract: A method and computer system for dynamically selecting an optimal synchronization mechanism for a data structure in a multiprocessor environment. The method determines a quantity of read-side and write-side acquisitions, and evaluates the data to determine an optimal mode for efficiently operating the computer system while maintaining reduced overhead. The method incorporates data received from the individual units within a central processing system, the quantity of write-side acquisitions in the system, and data which has been subject to secondary measures, such as formatives of digital filters. The data subject to secondary measures includes, but is not limited to, a quantity of read-side acquisitions, a quantity of write-side acquisitions, and a quantity of read-hold durations. Based upon the individual unit data and the system-wide data, including the secondary measures, the operating system may select the most efficient synchronization mechanism from among the mechanisms available.

Abstract: A general purposed operating system is modified to support hard real-time processing of hard real-time tasks. At least one processing unit in the operating system is designated as a hard real-time processing unit to process hard real-time tasks, and at least one processing unit in the operating system is designated as a non-hard real-time processing unit to process non-hard real-time tasks and designated non-deterministic processing steps. Hard real-time tasks assigned to the non-hard real-time processing unit may be transferred to the hard real-time processing unit, and tasks assigned to the hard real-time processing unit that are about to execute a non-deterministic processing step may be transferred to the non-hard real-time processing unit.

Abstract: A system and method is provided to support immediate freeing of a designated element from memory. Following a process of designating an element for removal from a data-structure, conditional limitations are used to determine if immediate freeing of the element from memory is available. The conditional limitations include determining that the instruction originates from a uniprocessor computer system. In addition, the conditional limitations include a determination as to whether a call_rcu primitive or synchronize_kernel primitive may be omitted, or whether the computer implemented instruction is operating in an interrupt handler. If the conditional limitations are met, the designated element may be immediately freed from memory.

Abstract: A technique for efficiently boosting the priority of a preemptable data reader in order to eliminate impediments to grace period processing that defers the destruction of one or more shared data elements that may be referenced by the reader until the reader is no longer capable of referencing the data elements. Upon the reader being subject to preemption or blocking, it is determined whether the reader is in a read-side critical section referencing any of the shared data elements. If it is, the reader's priority is boosted in order to expedite completion of the critical section. The reader's priority is subsequently decreased after the critical section has completed. In this way, delays in grace period processing due to reader preemption within the critical section, which can result in an out-of-memory condition, can be minimized efficiently with minimal processing overhead.

Abstract: A method, system and computer program product for avoiding unnecessary grace period token processing while detecting a grace period without atomic instructions in a read-copy update subsystem or other processing environment that requires deferring removal of a shared data element until pre-existing references to the data element are removed. Detection of the grace period includes establishing a token to be circulated between processing entities sharing access to the data element. A grace period elapses whenever the token makes a round trip through the processing entities. A distributed indicator associated with each processing entity indicates whether there is a need to perform removal processing on any shared data element. The distributed indicator is processed at each processing entity before the latter engages in token processing. Token processing is performed only when warranted by the distributed indicator.

Abstract: A user-level read-copy update (RCU) technique. A user-level RCU subsystem executes within threads of a user-level multithreaded application. The multithreaded application may include reader threads that read RCU-protected data elements in a shared memory and updater threads that update such data elements. The reader and updater threads may be preemptible and comprise signal handlers that process signals. Reader registration and unregistration components in the RCU subsystem respectively register and unregister the reader threads for RCU critical section processing. These operations are performed while the reader threads remain preemptible and with their signal handlers being operational.

Abstract: A technique for optimizing grace period detection following a data element update operation that affects preemptible data readers. A determination is made whether the data processing system is a uniprocessor system or a multiprocessor system. Grace period detection processing is performed using a first grace period detection technique if the data processing system is a multiprocessor system. Grace period detection processing is performed using a second grace period detection technique if the data processing system is a uniprocessor system. The grace period detection processing according to either technique determines the end of a grace period in which readers that are subject to preemption have passed through a quiescent state and cannot be maintaining references to the pre-update view of the shared data.

Abstract: A technique for realtime-safe detection of a grace period for deferring the destruction of a shared data element until pre-existing references to the data element have been removed. A per-processor read/write lock is established for each of one or more processors. When reading a shared data element at a processor, the processor's read/write lock is acquired for reading, the shared data element is referenced, and the read/write lock that was acquired for reading is released. When starting a new grace period, all of the read/write locks are acquired for writing, a new grace period is started, and all of the read/write locks are released.

Abstract: Dimensions of each physical object to be moved from an original physical site to a destination physical site are at least approximately determined. Each physical object is tagged with an identifier. A virtual layout of the destination physical site and the dimensions and the identifier of each physical object are input into a computer program. A user-specified location of where within the destination physical site each physical object is to be placed when moved to the destination physical site is input using the computer program, based on the virtual layout of the destination physical site and the dimensions and the identifier of each physical object. At the destination physical site, each physical object is looked up using the identifier of the physical object to determine the user-specified location of where to place the physical object within the destination physical site.

Abstract: A method, system and computer program product for supporting concurrent updates to a shared data element group while preserving group integrity on behalf of one or more readers that are concurrently referencing group data elements without using locks or atomic instructions. Two or more updaters may be invoked to generate new group data elements. Each new data element created by the same updater is assigned a new generation number that is different than a global generation number associated with the data element group and which allows a reader of the data element group to determine whether the new data element is a correct version for the reader. The new generation numbers are different for each updater and assigned according to an order in which the updaters respectively begin update operations.

Abstract: A technique for low-power detection of a grace period for deferring the destruction of a shared data element until pre-existing references to the data element have been removed. A grace period processing action is implemented that requires a response from a processor that may be running a preemptible reader of said shared data element before further grace period processing can proceed. A power and reader status of the processor is also determined. Grace period processing may proceed despite the absence of a response from the processor if the power and reader status indicates that an actual response from the processor is unnecessary.

Abstract: Utilizing a hardware transactional approach to execute a code section by employing pseudo-transactions, after initially utilizing software locking, is disclosed. A method is disclosed that utilizes a software approach to locking memory to execute a code section relating to memory. The software approach employs a pseudo-transaction to determine whether a hardware approach to transactional memory to execute the threshold would have been successful. Where the hardware approach to transactional memory to execute the code section satisfies a threshold based on success of at least the pseudo-transaction, the method subsequently utilizes the hardware approach to execute the code section. The hardware approach may include starting a transaction inclusive of the code section, conditionally executing the transaction, and, upon successfully completing the transaction, committing execution of the transaction to the memory to which the code section relates.

Abstract: A method for reducing power consumption in integrated devices is provided. The method comprising: locating a plurality of unused blocks of memory and a plurality of used blocks of memory in a memory device tlhrough a tracking mechanism; performing a refresh operation on the plurality of used blocks of memory at a constant frequency and suppressing the refresh operation on the plurality of unused blocks of memory through a memory controller; and suppressing error correction codes or parity errors on at least one of the plurality of unused blocks of memory when the at least one of the plurality of unused blocks of memory is accessed through the memory controller.

Abstract: A computing system is provided with real-time capabilities so that the system is capable of running applications such that one or more real-time criteria are satisfied. An interrupt architecture of the computing system is disabled. The interrupt architecture generates interrupts sent to a firmware of the computing system in response to events. A different architecture is substituted within the computing system for the interrupt architecture. The different architecture is responsive to the events without violating the real-time criteria. In response to the events occurring, the different architecture causes one or more corrective actions to be performed.