Patents by Inventor Paul E. McKenney

Paul E. McKenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8176489
    Abstract: A method, apparatus and program storage device for performing a return/rollback process for RCU-protected data structures is provided that includes checking a user-level state of a preempted thread having a RCU read-side critical section, and executing the critical section of the thread after preemption when the user-level state of the thread indicates execution, otherwise returning to a point of preemption, resuming execution of the thread and disabling checking the user-level state when the user-level state of the thread indicates return.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Robert T. Bauer, Paul E. McKenney, Paul F. Russell
  • Publication number: 20120079301
    Abstract: A technique for making a free-running grace period counter safe against lengthy low power state processor sojourns. The grace period counter tracks grace periods that determine when processors that are capable executing read operations have passed through a quiescent state that guarantees the readers will no longer maintain references to shared data. Periodically, one or more processors may be placed in a low power state in which the processors discontinue performing grace period detection operations. Such processors may remain in the low power state for a complete cycle of the grace period counter. This scenario can potentially disrupt grace period detection operations if the processors awaken to see the same grace period counter value. To rectify this situation, processors in a low power state may be periodically awakened at a predetermined point selected prevent the low power state from extending for an entire roll over of the grace period counter.
    Type: Application
    Filed: September 27, 2010
    Publication date: March 29, 2012
    Applicant: International Business Machines Corporation
    Inventor: Paul E. McKenney
  • Patent number: 8126843
    Abstract: A system, method and computer program product for synchronizing updates to shared mutable data in a clustered data processing system. A data element update operation is performed at each node of the cluster while preserving a pre-update view of the shared mutable data, or an associated operational mode, on behalf of readers that may be utilizing the pre-update view. A request is made for detection of a grace period, and grace period detection processing is performed for detecting when the cluster-wide grace period has occurred. When it does, a deferred action associated with the update operation it taken, such as removal of a pre-update view of the data element or termination of an associated mode of operation.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Julian Satran
  • Publication number: 20120047140
    Abstract: A system, method and computer program product for synchronizing updates to shared mutable data in a clustered data processing system. A data element update operation is performed at each node of the cluster while preserving a pre-update view of the shared mutable data, or an associated operational mode, on behalf of readers that may be utilizing the pre-update view. A request is made for detection of a grace period, and grace period detection processing is performed for detecting when the cluster-wide grace period has occurred. When it does, a deferred action associated with the update operation it taken, such as removal of a pre-update view of the data element or termination of an associated mode of operation.
    Type: Application
    Filed: October 31, 2011
    Publication date: February 23, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul E. McKenney, Julian Satran
  • Publication number: 20110283082
    Abstract: A system, method and computer program product for resizing a hash table while supporting hash table scalability and concurrency. The hash table has one or more hash buckets each containing one or more items that are chained together in a linked list. Each item in the hash table is processed to determine if the item requires relocation from a first bucket associated with a first table size to second bucket associated with a second table size. If the item requires relocation, it is linked to the second bucket without moving or copying the item in memory. The item is unlinked from the first bucket after waiting until there is no current hash table reader whose search of the hash table could be affected by the unlinking, again without moving or copying the item in memory.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul E. McKenney, Joshua A. Triplett
  • Patent number: 8055918
    Abstract: A technique for low-power detection of a grace period for deferring the destruction of a shared data element until pre-existing references to the data element have been removed. A grace period processing action is implemented that requires a response from a processor that may be running a preemptible reader of said shared data element before further grace period processing can proceed. A power and reader status of the processor is also determined. Grace period processing may proceed despite the absence of a response from the processor if the power and reader status indicates that an actual response from the processor is unnecessary.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Joshua A. Triplett
  • Patent number: 8055860
    Abstract: Read-copy-update (RCU) is performed within real-time and other types of systems, such that memory barrier usage within RCU is reduced. A computerized system includes processors, memory, updaters, and readers. The updaters update contents of a section of the memory by using first and second sets of per-processor counters, first and second sets of per-processor need-memory-barrier bits, and a global flip-counter bit. The global flip-counter bit specifies which of the first or second set of the per-processor counters and the per-processor need-memory-barrier bits is a current set, and which is a last set. The readers read the contents of the section of the memory by using the first and second sets of per-processor counters, the first and second sets of per-processor need-memory-barrier bits, and the global flip-counter bit, in a way that significantly reduces the need for memory barriers during such read operations.
    Type: Grant
    Filed: January 27, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Suparna Bhattacharya
  • Patent number: 8020160
    Abstract: A user-level read-copy update (RCU) technique. A user-level RCU subsystem executes within threads of a user-level multithreaded application. The multithreaded application may include reader threads that read RCU-protected data elements in a shared memory and updater threads that update such data elements. The reader and updater threads may be preemptible and comprise signal handlers that process signals. Reader registration and unregistration components in the RCU subsystem respectively register and unregister the reader threads for RCU critical section processing. These operations are performed while the reader threads remain preemptible and with their signal handlers being operational.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: September 13, 2011
    Assignee: International Business Machines Corporation
    Inventor: Paul E. McKenney
  • Patent number: 7987166
    Abstract: Atomic renaming and moving of data files, while permitting lock-free look-ups to the data files, is disclosed. A temporary record may be created within a hash chain encompassing a record for a data file and corresponding to a location of the data file within a computer file system. The temporary record is linked within the hash chain so that the temporary record points to the same records to which the record for the data file points. The record for the data file is renamed with a new name, and/or moved to a new location within the computer file system, and the temporary record is removed from the hash chain. Before the temporary record is removed, look-ups of the data file resolve to the temporary record, the temporary record causing the look-ups to wait until the record for the data file has been renamed and/or moved and the temporary record removed.
    Type: Grant
    Filed: April 22, 2007
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Dipankar Sarma, Maneesh Soni
  • Patent number: 7979617
    Abstract: A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. At least some of the processors in the system are organized into a hierarchy, and process an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. To prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Benedict Jackson, Ramakrishnan Rajamony, Ronald L. Rockhold
  • Patent number: 7971243
    Abstract: A method and apparatus for restricting access of an application to computer hardware. The apparatus includes both an authentication module and a validation module. The authentication module is within the trusted firmware layer. The purpose of the authentication module is to verify a cryptographic key presented by an application. The validation module is responsive to the authentication module and limits access of the application to the computer hardware. The authentication modules may be implemented in software through a firmware call, or through a hardware register of the computer.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Orran Y. Krieger, Boas Betzler
  • Publication number: 20110137962
    Abstract: A technique for applying hardware transaction memory to an arbitrarily large data structure is disclosed. A data updater traverses the data structure to locate an update point using a lockless synchronization technique that synchronizes the data updater with other updaters that may be concurrently updating the data structure. At the update point, the updater performs an update on the data structure using a hardware transactional memory transaction that operates at the update point.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 9, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul E. McKenney, Maged M. Michael
  • Patent number: 7953708
    Abstract: A technique for optimizing grace period detection following a data element update operation that affects preemptible data readers. A determination is made whether the data processing system is a uniprocessor system or a multiprocessor system. Grace period detection processing is performed using a first grace period detection technique if the data processing system is a multiprocessor system. Grace period detection processing is performed using a second grace period detection technique if the data processing system is a uniprocessor system. The grace period detection processing according to either technique determines the end of a grace period in which readers that are subject to preemption have passed through a quiescent state and cannot be maintaining references to the pre-update view of the shared data.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Joshua A. Triplett
  • Patent number: 7953778
    Abstract: A method, system and computer program product for supporting concurrent updates to a shared data element group while preserving group integrity on behalf of one or more readers that are concurrently referencing group data elements without using locks or atomic instructions. Two or more updaters may be invoked to generate new group data elements. Each new data element created by the same updater is assigned a new generation number that is different than a global generation number associated with the data element group and which allows a reader of the data element group to determine whether the new data element is a correct version for the reader. The new generation numbers are different for each updater and assigned according to an order in which the updaters respectively begin update operations.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Jonathan Walpole
  • Patent number: 7934062
    Abstract: An improved reader-writer locking for synchronizing access to shared data. When writing the shared data, a writer flag is set and a lock is acquired on the shared data. The shared data may be accessed following the expiration of a grace period and a determination that there are no data readers accessing the shared data. When reading the shared data, the writer flag is tested that indicates whether a data writer is attempting to access the shared data. If the writer flag is not set, the shared data is accessed using a relatively fast read mechanism. If the writer flag is set, the shared data is accessed using a relatively slow read mechanism.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: April 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Vaddagiri Srivatsa, Gautham R. Shenoy
  • Patent number: 7904436
    Abstract: A technique for realtime-safe detection of a grace period for deferring the destruction of a shared data element until pre-existing references to the data element have been removed. A pair of counters is established for each of one or more processors. A global counter selector determines which counter of each per-processor counter pair is a current counter. When reading a shared data element at a processor, the processor's current counter is incremented. Following counter incrementation, the processor's counter pair is tested for reversal to ensure that the incremented counter is still the current counter. If a counter reversal has occurred, such that the incremented counter is no longer current, the processor's other counter is incremented. Following referencing of the shared data element, any counter that remains incremented is decremented.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventor: Paul E. McKenney
  • Patent number: 7904438
    Abstract: A flag and a wait period are used to guarantee that readers of two data values see the updated first value before they see the updated second value, where the second value has to be updated after the first value is updated and thus is dependent on the first value. The first value is updated, and a flag associated with the first data value is set. The flag effectively prevents further updating of the first data value until it has been cleared. A length of time is waited for, such that any reading of the first data value and the second data value is guaranteed to not see the second data value as updated unless the first data value is also seen as updated. The flag is then cleared, such that further updating of the first data value can again occur. The second data value is finally updated.
    Type: Grant
    Filed: August 22, 2010
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventor: Paul E. McKenney
  • Publication number: 20110055183
    Abstract: A technique for reducing reader overhead when referencing a shared data element while facilitating realtime-safe detection of a grace period for deferring destruction of the shared data element. The grace period is determined by a condition in which all readers that are capable of referencing the shared data element have reached a quiescent state subsequent to a request for a quiescent state. Common case local quiescent state tracking may be performed using only local per-reader state information for all readers that have not blocked while in a read-side critical section in which the data element is referenced. Uncommon case non-local quiescent state tracking may be performed using non-local multi-reader state information for all readers that have blocked while in their read-side critical section. The common case local quiescent state tracking requires less processing overhead than the uncommon case non-local quiescent state tracking.
    Type: Application
    Filed: September 2, 2009
    Publication date: March 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Paul E. McKenney
  • Publication number: 20110055630
    Abstract: A technique for safely rolling back transactional memory transactions without impacting concurrent readers of the uncommitted transaction data. An updater uses a transactional memory technique to perform an data update on data that is shared with a reader. The update is implemented as a transaction in which the updated data is initially uncommitted due to the transaction being subject to roll back. The reader is allowed to perform a data read on the uncommitted data during the transaction. Upon a rollback of the transaction, reclamation of memory locations used by the uncommitted data is deferred until a grace period has elapsed after which the reader can no longer be referencing the uncommitted data.
    Type: Application
    Filed: September 3, 2009
    Publication date: March 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul E. McKenney, Joshua A. Triplett
  • Patent number: 7873612
    Abstract: A system, method and computer program product for atomically moving a shared list element from a first list location to a second list location includes inserting a placeholder element at the second list location to signify to readers that a move operation is underway, removing the shared list element from the first list location, re-identifying the list element to reflect its move from the first list location to the second list location, inserting it at the second list location and unlinking the placeholder element. A deferred removal of the placeholder element is performed following a period in which readers can no longer maintain references thereto. A method, system and computer program product are additionally provided for performing a lookup of a target list element that is subject to being atomically moved from a first list to a second list.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: January 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Orran Y. Krieger, Dipankar Sarma, Maneesh Soni