Patents by Inventor Paul Enquist

Paul Enquist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10204893
    Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: February 12, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
  • Publication number: 20170338214
    Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.
    Type: Application
    Filed: May 19, 2016
    Publication date: November 23, 2017
    Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
  • Publication number: 20080093747
    Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 24, 2008
    Applicant: ZIPTRONIX
    Inventors: Paul Enquist, Gaius Fountain
  • Publication number: 20080063878
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 13, 2008
    Applicant: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Fountain, Paul Enquist
  • Publication number: 20080061419
    Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 13, 2008
    Applicant: ZIPTRONIX
    Inventors: Paul Enquist, Gaius Fountain
  • Publication number: 20080061418
    Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 13, 2008
    Applicant: ZIPTRONIX
    Inventors: Paul Enquist, Gaius Fountain
  • Publication number: 20080053959
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 6, 2008
    Applicant: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Fountain, Paul Enquist
  • Publication number: 20070232023
    Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.
    Type: Application
    Filed: June 5, 2007
    Publication date: October 4, 2007
    Applicant: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Paul Enquist, Anthony Rose
  • Publication number: 20070037379
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface.
    Type: Application
    Filed: August 11, 2005
    Publication date: February 15, 2007
    Applicant: Ziptronix
    Inventors: Paul Enquist, Gaius Fountain, Qin-Yi Tong
  • Publication number: 20060292744
    Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.
    Type: Application
    Filed: September 1, 2006
    Publication date: December 28, 2006
    Applicant: ZIPTRONIX
    Inventors: Paul Enquist, Gaius Fountain
  • Publication number: 20050194668
    Abstract: A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.
    Type: Application
    Filed: March 5, 2004
    Publication date: September 8, 2005
    Applicant: Ziptronix, Inc
    Inventors: Paul Enquist, Gaius Fountain, Carl Petteway
  • Publication number: 20050181542
    Abstract: A method of connecting elements such as semiconductor devices and a device having connected elements such as semiconductor devices. A first element having a first contact structure is bonded to a second element having a second contact structure. A single mask is used to form a via in the first element to expose the first contact and the second contact. The first contact structure is used as a mask to expose the second contact structure. A contact member is formed in contact with the first and second contact structures. The first contact structure may have an aperture or gap through which the first and second contact structures are connected. A back surface of the first contact structure may be exposed by the etching.
    Type: Application
    Filed: December 10, 2004
    Publication date: August 18, 2005
    Applicant: Ziptronix, Inc.
    Inventor: Paul Enquist
  • Publication number: 20050161795
    Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.
    Type: Application
    Filed: March 22, 2005
    Publication date: July 28, 2005
    Applicant: Ziptronix
    Inventors: Qin-Yi Tong, Paul Enquist, Anthony Rose
  • Publication number: 20050079712
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Application
    Filed: August 9, 2004
    Publication date: April 14, 2005
    Applicant: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Gaius Fountain, Paul Enquist
  • Publication number: 20050009246
    Abstract: A method for providing encapsulation of an electronic device which obtains an encapsulating member configured to enclose the electronic device, prepares a surface of the encapsulating member for non-adhesive direct bonding, prepares a surface of a device carrier including the electronic device for non-adhesive direct bonding, and bonds the prepared surface of the encapsulating member to the prepared surface of the device carrier to form an encapsulation of the electronic device. As such, an encapsulated electronic device results which includes the device carrier having a first bonding region encompassing the electronic device, includes the encapsulating member having at least one relief preventing contact between the electronic device and the encapsulating member and having a second bonding region bonded to the first bonding region of the device carrier, and includes a non-adhesive direct bond formed between the first and second bonding regions thereby to form an encapsulation of the electronic device.
    Type: Application
    Filed: August 9, 2004
    Publication date: January 13, 2005
    Applicant: Ziptronix, Inc.
    Inventors: Paul Enquist, Qin-Yi Tong, Gaius Fountain, Robert Markunas
  • Patent number: 6756281
    Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: June 29, 2004
    Assignee: Ziptronix
    Inventor: Paul Enquist
  • Patent number: 6740909
    Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: May 25, 2004
    Assignee: Ziptronix, Inc.
    Inventor: Paul Enquist
  • Patent number: 6368930
    Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: April 9, 2002
    Assignee: Ziptronix
    Inventor: Paul Enquist
  • Publication number: 20010019873
    Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.
    Type: Application
    Filed: April 2, 2001
    Publication date: September 6, 2001
    Applicant: Research Triangle Institute
    Inventor: Paul Enquist
  • Patent number: 6242794
    Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: June 5, 2001
    Assignee: Research Triangle Institute
    Inventor: Paul Enquist