Patents by Inventor Paul Enquist
Paul Enquist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050194668Abstract: A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.Type: ApplicationFiled: March 5, 2004Publication date: September 8, 2005Applicant: Ziptronix, IncInventors: Paul Enquist, Gaius Fountain, Carl Petteway
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Publication number: 20050181542Abstract: A method of connecting elements such as semiconductor devices and a device having connected elements such as semiconductor devices. A first element having a first contact structure is bonded to a second element having a second contact structure. A single mask is used to form a via in the first element to expose the first contact and the second contact. The first contact structure is used as a mask to expose the second contact structure. A contact member is formed in contact with the first and second contact structures. The first contact structure may have an aperture or gap through which the first and second contact structures are connected. A back surface of the first contact structure may be exposed by the etching.Type: ApplicationFiled: December 10, 2004Publication date: August 18, 2005Applicant: Ziptronix, Inc.Inventor: Paul Enquist
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Publication number: 20050161795Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.Type: ApplicationFiled: March 22, 2005Publication date: July 28, 2005Applicant: ZiptronixInventors: Qin-Yi Tong, Paul Enquist, Anthony Rose
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Publication number: 20050079712Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.Type: ApplicationFiled: August 9, 2004Publication date: April 14, 2005Applicant: Ziptronix, Inc.Inventors: Qin-Yi Tong, Gaius Fountain, Paul Enquist
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Publication number: 20050009246Abstract: A method for providing encapsulation of an electronic device which obtains an encapsulating member configured to enclose the electronic device, prepares a surface of the encapsulating member for non-adhesive direct bonding, prepares a surface of a device carrier including the electronic device for non-adhesive direct bonding, and bonds the prepared surface of the encapsulating member to the prepared surface of the device carrier to form an encapsulation of the electronic device. As such, an encapsulated electronic device results which includes the device carrier having a first bonding region encompassing the electronic device, includes the encapsulating member having at least one relief preventing contact between the electronic device and the encapsulating member and having a second bonding region bonded to the first bonding region of the device carrier, and includes a non-adhesive direct bond formed between the first and second bonding regions thereby to form an encapsulation of the electronic device.Type: ApplicationFiled: August 9, 2004Publication date: January 13, 2005Applicant: Ziptronix, Inc.Inventors: Paul Enquist, Qin-Yi Tong, Gaius Fountain, Robert Markunas
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Patent number: 6756281Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.Type: GrantFiled: March 14, 2002Date of Patent: June 29, 2004Assignee: ZiptronixInventor: Paul Enquist
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Patent number: 6740909Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.Type: GrantFiled: April 2, 2001Date of Patent: May 25, 2004Assignee: Ziptronix, Inc.Inventor: Paul Enquist
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Patent number: 6368930Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.Type: GrantFiled: October 2, 1998Date of Patent: April 9, 2002Assignee: ZiptronixInventor: Paul Enquist
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Publication number: 20010019873Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.Type: ApplicationFiled: April 2, 2001Publication date: September 6, 2001Applicant: Research Triangle InstituteInventor: Paul Enquist
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Patent number: 6242794Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.Type: GrantFiled: May 13, 1999Date of Patent: June 5, 2001Assignee: Research Triangle InstituteInventor: Paul Enquist
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Patent number: 6107151Abstract: A heterojunction bipolar transistor structure grown with organometallic vapor phase epitaxy (OVMPE) which uses zinc as the base dopant. The HBT structure has eight layers grown on a substrate, including n-type doped first, second, third, fifth, sixth, seventh, and eighth layers and a p-type zinc doped fourth layer. The first layer is a thicker, moderately doped n-type layer compared to the thinner, higher doped n-type second layer. The seventh layer is a thicker, moderately doped n-type layer compared to the thinner, higher doped n-type eighth layer. In addition, some or perhaps all of the layers have a high V/III ratio of 10-100 used to increase the gallium vacancies and reduce the diffusion of zinc from the base layer. Further, annealing of the structure is performed during growth to minimize gallium interstitials and to inhibit the diffusion of zinc.Type: GrantFiled: May 8, 1998Date of Patent: August 22, 2000Assignee: Research Triangle InstituteInventor: Paul Enquist