Abstract: A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups, associated with a plurality of latches to be placed in the chip design, is determined. Based on the set of chip design constraints and the set of checking groups, a placement scheme for the plurality of latches is selected. The method places the plurality of latches within the chip design based on the placement scheme and the set of checking groups.

Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

Abstract: Embodiments are provided for enhanced initial global placement in a circuit design in a computing system by a processor. A wire length minimization may be determined based on maximum population density constraints as a single player game theory for global placement of an integrated circuit.

Abstract: Embodiments are provided for providing enhanced routing in a computing system by a processor. One or more of a plurality of short nets in a cell of an integrated circuit may be aligned for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold.

Abstract: Embodiments are provided for providing power staple avoidance during routing in a computing system by a processor. One or more transistor gates may be shifted in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, where the circuit row is partitioned into segments based on one or more fixed objects.

Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

Abstract: To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

Abstract: A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

Abstract: For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.

Abstract: To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

Abstract: A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.

Abstract: A design system accesses at least one placement template for at least one structured soft block composed of a pre-defined set of cells with relative placement information for the pre-defined set of cells. The design system optimizes implementation of the at least one structured soft block by propagating constants while preserving relative placement structure of the pre-defined set of cells within each at least one structured soft block according to the respective at least one placement template accessed for the at least one structured soft block.

Abstract: For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.

Abstract: A system and method of performing model-based refinement of a placement of components in integrated circuit generation select one of the components as a candidate component and postulate a move of the candidate component from an original position to a new position. The method includes defining nets associated with the candidate component. An initial perimeter and a new perimeter associated with each of the one or more nets are defined. The initial perimeter includes the candidate component at its original position and the new perimeter includes the candidate component at its new position. The method includes quantifying a change from the initial perimeter and the new perimeter and the original position and the new position, and obtaining a model of wires interconnecting the candidate component to the components of each of the nets. A result of the placement is provided for manufacture of the integrated circuit.

Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.

Abstract: A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.

Abstract: A design system accesses at least one placement template for at least one structured soft block composed of a pre-defined set of cells with relative placement information for the pre-defined set of cells. The design system optimizes implementation of the at least one structured soft block by propagating constants while preserving relative placement structure of the pre-defined set of cells within each at least one structured soft block according to the respective at least one placement template accessed for the at least one structured soft block.

Abstract: The performance of a computer performing electronic design analysis is improved by representing a putative circuit design as a set of movable blocks of predetermined size which must fit into a bounding box (said blocks include a plurality of subsets to be interconnected by wires) and initially placing the set of blocks by quadratic initialization. Each of the blocks has first and second coordinates and weights are assigned to nets connecting those of the blocks within the subsets, the quadratic initialization in turn includes determining a cost of each of the nets connecting any two of the blocks within the subsets as one-half of a sum of squares of distances between the any two of the blocks; and minimizing a total cost over all of the nets to determine an initial placement of the set of blocks. Analytical placement is then carried out based on the initial quadratic placement.

Abstract: The performance of a computer performing electronic design analysis is improved by representing a putative circuit design as a set of movable blocks of predetermined size which must fit into a bounding box (said blocks include a plurality of subsets to be interconnected by wires) and initially placing the set of blocks by quadratic initialization. Each of the blocks has first and second coordinates and weights are assigned to nets connecting those of the blocks within the subsets, the quadratic initialization in turn includes determining a cost of each of the nets connecting any two of the blocks within the subsets as one-half of a sum of squares of distances between the any two of the blocks; and minimizing a total cost over all of the nets to determine an initial placement of the set of blocks. Analytical placement is then carried out based on the initial quadratic placement.

Abstract: A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.