Patents by Inventor Paul G. Villarrubia
Paul G. Villarrubia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8799846Abstract: Embodiments of the disclosure relate to methods for facilitating the design of a clock grid in an integrated circuit. The method includes propagating a chip level virtual grid across a multi-level hierarchy of the integrated circuit and customizing the grid at each macro to create a customized virtual grid for each macro. The method further includes propagating the customized virtual grid for each of the plurality of macros to one of a plurality of units and customizing the chip level virtual grid at each of the plurality of units to create the customized virtual grid for each of the plurality of units. The method also includes propagating the customized virtual grid for each of the plurality of units to the chip level and combining the plurality of customized virtual grids to form the clock grid for the integrated circuit.Type: GrantFiled: March 15, 2013Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Joseph N. Kozhaya, Daniel R. Menard, Susan R. Sanicky, Amanda C. Venton, Paul G. Villarrubia, Michael H. Wood
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Patent number: 8782584Abstract: A computer implemented method for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.Type: GrantFiled: May 24, 2013Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Charles J Alpert, Zhuo D Li, Gi-Joon Nam, Shyam Ramji, Lakshmi N Reddy, Jarrod A Roy, Taraneh E Taghavi, Paul G Villarrubia, Natarajan Viswanathan
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Publication number: 20140149957Abstract: A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design.Type: ApplicationFiled: November 29, 2012Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Chin Ngai Sze, Paul G. Villarrubia, Natarajan Viswanathan
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Publication number: 20140033154Abstract: Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.Type: ApplicationFiled: October 4, 2013Publication date: January 30, 2014Applicant: International Business Machines CorporationInventors: Gi-Joon Nam, Shyam Ramji, Taraneh Taghavi, Paul G. Villarrubia
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Publication number: 20130346938Abstract: A computer implemented method for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.Type: ApplicationFiled: May 24, 2013Publication date: December 26, 2013Applicant: International Business Machines CorporationInventors: Charles J Alpert, Zhuo D Li, Gi-Joon Nam, Shyam Ramji, Lakshmi N Reddy, Jarrod A Roy, Taraneh E Taghavi, Paul G Villarrubia, Natarajan Viswanathan
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Publication number: 20130326455Abstract: An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Applicant: International Business Machines CorporationInventors: Charles J. Alpert, Gi-Joon Nam, Chin Ngai Sze, Paul G. Villarrubia, Natarajan Viswanathan
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Patent number: 8578315Abstract: Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.Type: GrantFiled: July 17, 2012Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Gi-Joon Nam, Shyam Ramji, Taraneh Taghavi, Paul G. Villarrubia
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Patent number: 8555221Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.Type: GrantFiled: August 20, 2012Date of Patent: October 8, 2013Assignee: International Business Machines CorporationInventors: Michael D. Moffitt, Matyas A. Sustik, Paul G. Villarrubia
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Patent number: 8495534Abstract: A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.Type: GrantFiled: June 8, 2010Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Charles J. Alpert, Zhuo D. Li, Gi-Joon Nam, Shyam Ramji, Lakshmi N. Reddy, Jarrod A. Roy, Taraneh E. Taghavi, Paul G. Villarrubia, Natarajan Viswanathan
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Patent number: 8370782Abstract: A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit.Type: GrantFiled: June 25, 2010Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Chuck Alpert, Zhuo Li, Michael David Moffitt, Chin Ngai Sze, Paul G Villarrubia
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Patent number: 8347257Abstract: A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.Type: GrantFiled: June 8, 2010Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Charles J. Alpert, Andrew D. Huber, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Jarrod A. Roy, Taraneh E. Taghavi, Gustavo E. Tellez, Paul G. Villarrubia, Natarajan Viswanathan
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Publication number: 20120317527Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.Type: ApplicationFiled: August 20, 2012Publication date: December 13, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael D. Moffitt, Matyas A. Sustik, Paul G. Villarrubia
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Patent number: 8327304Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.Type: GrantFiled: November 18, 2010Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Michael D. Moffitt, Matyas A. Sustik, Paul G. Villarrubia
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Publication number: 20120297355Abstract: A method, system, and computer program product for whitespace creation and preservation in the design of an integrated circuit (IC) are provided in the illustrative embodiments. A first estimate is formed by estimating an amount of whitespace that is needed to reduce a congestion value of a congested area of the design to a threshold value. A set of virtual filler cells is added to the congested area, wherein adding the set of virtual filler cells does not add actual whitespace cells to the congested area but reduces the congested area by at least the first estimate. A virtual filler cell in the set of virtual filler cells is replaced with a corresponding real filler cell. A determination is made whether the design has improved. A final placement solution is created when the design has not improved.Type: ApplicationFiled: May 20, 2011Publication date: November 22, 2012Applicant: International Business Machines CorporationInventors: Charles Jay Alpert, Gi-Joon Nam, Shyam Ramji, Jarrod Alexander Roy, Paul G. Villarrubia, Natarajan Viswanathan
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Publication number: 20120284733Abstract: Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.Type: ApplicationFiled: July 17, 2012Publication date: November 8, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gi-Joon Nam, Shyam Ramji, Taraneh Taghavi, Paul G. Villarrubia
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Patent number: 8245173Abstract: Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.Type: GrantFiled: January 26, 2009Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Gi-Joon Nam, Shyam Ramji, Taraneh Taghavi, Paul G. Villarrubia
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Publication number: 20120131530Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.Type: ApplicationFiled: November 18, 2010Publication date: May 24, 2012Applicant: International Business Machines CorporationInventors: MICHAEL D. MOFFITT, Matyas A. Sustik, Paul G. Villarrubia
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Publication number: 20110320992Abstract: A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit.Type: ApplicationFiled: June 25, 2010Publication date: December 29, 2011Applicant: International Business Machines CorporationInventors: Chuck ALPERT, Zhuo Li, Michael David Moffitt, Chin Ngai Sze, Paul G. Villarrubia
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Publication number: 20110302544Abstract: A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.Type: ApplicationFiled: June 8, 2010Publication date: December 8, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Lakshmi N. Reddy, Jarrod A. Roy, Taraneh Taghavi, Paul G. Villarrubia, Natarajan Viswanathan
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Publication number: 20110302545Abstract: A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.Type: ApplicationFiled: June 8, 2010Publication date: December 8, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles J. Alpert, Andrew D. Huber, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Jarrod A. Roy, Taraneh Taghavi, Gustavo E. Tellez, Paul G. Villarrubia, Natarajan Viswanathan