Patents by Inventor Paul Henry
Paul Henry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12293913Abstract: Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.Type: GrantFiled: December 22, 2021Date of Patent: May 6, 2025Assignee: Intel CorporationInventors: Gurpreet Singh, Richard E. Schenker, Nityan Labros Nair, Nafees A. Kabir, Gauri Nabar, Eungnak Han, Xuanxuan Chen, Tayseer Mahdi, Brandon Jay Holybee, Charles Henry Wallace, Paul A. Nyhus, Manish Chandhok, Florian Gstrein
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Publication number: 20250139859Abstract: Disclosed are systems, computer-program products, and computer-implemented methods for the automatic estimation of geographic boundaries. Implementations of the foregoing may be useful for automatedly determining the geographic boundary of a community. In some embodiments, a computing device may receive birth location data related to the community. Enriched birth locations for the community may be determined based on likelihood metrics. An estimated geographic boundary of the community may be determined. The estimated geographic boundary may correspond to a probability density of the enriched birth locations represented using the geographical coordinates. A graphical user interface may present a map and the estimated geographic boundary of the community overlaying the map.Type: ApplicationFiled: September 6, 2024Publication date: May 1, 2025Inventors: Luong Ruiz, Samuel Henry Dauphinee, Paul Rawlins, Oleksii Mukhin, Jeremy Allen Casper
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Patent number: 12266527Abstract: Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.Type: GrantFiled: December 22, 2021Date of Patent: April 1, 2025Assignee: Intel CorporationInventors: Gurpreet Singh, Nityan Labros Nair, Nafees A. Kabir, Eungnak Han, Xuanxuan Chen, Brandon Jay Holybee, Charles Henry Wallace, Paul A. Nyhus, Manish Chandhok, Florian Gstrein, David Nathan Shykind, Thomas Christopher Hoff
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Publication number: 20250098976Abstract: Systems and methods are provided for processing a set of multiple serially acquired magnetic resonance spectroscopy (MRS) free induction decay (FID) frames from a multi-frame MRS acquisition series from a region of interest (ROI) in a subject, and for providing a post-processed MRS spectrum. Processing parameters are dynamically varied while measuring results to determine the optimal post-processed results. Spectral regions opposite water from chemical regions of interest are evaluated and used in at least one processing operation. Frequency shift error is estimated via spectral correlation between free induction decay (FID) frames and a reference spectrum. Multiple groups of FID frames within the acquired set are identified to different phases corresponding with a phase step cycle of the acquisition. Baseline correction is also performed via rank order filter (ROF) estimate and a polynomial fit.Type: ApplicationFiled: June 28, 2024Publication date: March 27, 2025Inventors: James Clayton Peacock, III, John Patrick Claude, Paul Henry Kane, Ricardo Dario Pradenas
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Publication number: 20250072625Abstract: A bed base kit includes left and right side rails and a head and foot rails. The first end of the left side rail interconnects with the left end of the head rail at a left head joint. The first end of the right side rail interconnects with the right end of the head rail at a right head joint. The second end of the left side rail interconnects with the left end of the foot rail at a left foot joint. The second end of the right side rail interconnects with the right end of the foot rail at a right foot joint. The joints have male and female interconnect elements cooperatively operable to interconnect the respective ends. A center rail may also be provided for supporting a midportion of slats, with the center rail having ends that interconnect with the head and foot rail.Type: ApplicationFiled: August 30, 2024Publication date: March 6, 2025Inventors: Lee Henry, Paul Orest Sharon, Anthony Martin, Eric Brubacker, Mark Burkholder, Benjamin Burkholder
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Publication number: 20250036699Abstract: A level of busyness of a public place may be represented using content specific to the public place. Images, video, audio, or other content captured at the public place is correlated with busyness information for the public place at the time of capture. Representative content is selected and stored based on a number of factors such as to minimize resources in storing and transmitting the content. The selected representative content may be provided in response to a user request for information related to the public place, such that the user receives an accurate portrayal of how the public place would look, sound, and/or feel at a given time.Type: ApplicationFiled: October 16, 2024Publication date: January 30, 2025Inventors: Ken Kawamoto, Kevin Kwok, Samuel G. Beckman, Winston Hsu, Christopher Davie, Paul Henry Sullivan, Rita Chow
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Publication number: 20250029915Abstract: Methods for fabricating an IC structure, e.g., for fabricating a metallization stack portion of an IC structure, as well as related semiconductor devices, are disclosed. An example fabrication method includes splitting metal lines that are supposed to be included at a tight pitch in a single metallization layer into two vertically-stacked layers (hence the term “vertical metal splitting”) by using helmets and wrap-around dielectric spacers. Metal lines split into two such layers may be arranged at a looser pitch in each layer, compared to the pitch at which metal lines of the same size would have to be arranged if there were included in a single layer. Increasing the pitch of metal lines may advantageously allow decreasing the parasitic metal-to-metal capacitance associated with the metallization stack.Type: ApplicationFiled: September 13, 2024Publication date: January 23, 2025Applicant: Intel CorporationInventors: Leonard P. Guler, Charles Henry Wallace, Paul A. Nyhus
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Patent number: 12147486Abstract: A level of busyness of a public place may be represented using content specific to the public place. Images, video, audio, or other content captured at the public place is correlated with busyness information for the public place at the time of capture. Representative content is selected and stored based on a number of factors such as to minimize resources in storing and transmitting the content. The selected representative content may be provided in response to a user request for information related to the public place, such that the user receives an accurate portrayal of how the public place would look, sound, and/or feel at a given time.Type: GrantFiled: December 30, 2021Date of Patent: November 19, 2024Assignee: Google LLCInventors: Ken Kawamoto, Kevin Kwok, Samuel G. Beckman, Winston Hsu, Christopher Davie, Paul Henry Sullivan, Rita Chow
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Publication number: 20240324892Abstract: An MR Spectroscopy (MRS) system and approach is provided for diagnosing painful and non-painful discs in chronic, severe low back pain patients (DDD-MRS). A DDD-MRS pulse sequence generates and acquires DDD-MRS spectra within intervertebral disc nuclei for later signal processing and diagnostic analysis. An interfacing DDD-MRS signal processor receives output signals of the DDD-MRS spectra acquired and is configured to optimize signal-to-noise ratio by an automated system that selectively conducts optimal channel selection, phase and frequency correction, and frame editing as appropriate for a given acquisition series. A diagnostic processor calculates a diagnostic value for the disc based upon a weighted factor set of criteria that uses MRS data extracted from the acquired and processed MRS spectra for multiple chemicals that have been correlated to painful vs. non-painful discs. A display provides an indication of results for analyzed discs as an overlay onto a MRI image of the lumbar spine.Type: ApplicationFiled: November 3, 2023Publication date: October 3, 2024Inventors: James Clayton Peacock, III, John Patrick Claude, Paul Henry Kane
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Patent number: 12097020Abstract: Systems and methods are provided for processing a set of multiple serially acquired magnetic resonance spectroscopy (MRS) free induction decay (FID) frames from a multi-frame MRS acquisition series from a region of interest (ROI) in a subject, and for providing a post-processed MRS spectrum. Processing parameters are dynamically varied while measuring results to determine the optimal post-processed results. Spectral regions opposite water from chemical regions of interest are evaluated and used in at least one processing operation. Frequency shift error is estimated via spectral correlation between free induction decay (FID) frames and a reference spectrum. Multiple groups of FID frames within the acquired set are identified to different phases corresponding with a phase step cycle of the acquisition. Baseline correction is also performed via rank order filter (ROF) estimate and a polynomial fit.Type: GrantFiled: March 27, 2023Date of Patent: September 24, 2024Assignee: ACLARION, INC.Inventors: James Clayton Peacock, III, John Patrick Claude, Paul Henry Kane, Ricardo Dario Pradenas
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Publication number: 20240311611Abstract: The present disclosure relates to a method for measuring a similarity between two graphs comprising: determining a feature vector for each of the two graphs; and calculating an estimated value of the similarity between the two graphs by comparing the two feature vectors, wherein, for each of the two graphs, determining a feature vector comprises: providing an array (120) of atoms arranged to model the graph (G1), wherein each atom of the array has a plurality of energy levels corresponding to at least a first reference state (a0) and at least a first excited state (a1); preparing the atoms of the array in the reference state (a0); applying an interaction sequence (137) to the array of atoms: detecting atoms of the array that are in the excited state (a1) to compute a value of an observable (O1) of the array of atoms; and determining a feature vector (f) based on a distribution of the plurality of values of said observable (O1_i).Type: ApplicationFiled: July 7, 2022Publication date: September 19, 2024Inventors: Loïc Henriet, Louis-Paul Henry, Constantin Dalyac, Slimane Thabet
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Publication number: 20240276632Abstract: A method of forming a flexible interconnect circuit is described. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.Type: ApplicationFiled: April 2, 2024Publication date: August 15, 2024Applicant: CelLink CorporationInventors: Kevin Michael Coakley, Malcolm Parker Brown, Dongao Yang, Michael Lawrence Miller, Paul Henry Lego
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Publication number: 20240228603Abstract: The present disclosure provides modified antibodies which contain an antibody or antibody fragment (AB) modified with a masking moiety (MM). Such modified antibodies can be further coupled to a cleavable moiety (CM), resulting in activatable antibodies (AAs), wherein the CM is capable of being cleaved, reduced, photolysed, or otherwise modified. AAs can exhibit an activatable conformation such that the AB is more accessible to a target after, for example, removal of the MM by cleavage, reduction, or photolysis of the CM in the presence of an agent capable of cleaving, reducing, or photolysing the CM. The disclosure further provides methods of making and using such modified antibodies and activatable antibodies.Type: ApplicationFiled: December 29, 2023Publication date: July 11, 2024Applicant: CytomX Therapeutics, Inc.Inventors: Nancy Elizabeth STAGLIANO, James William WEST, Kathryn KAMATH, Paul Henry BESSETTE, Fred GLUCK, Jason Gary SAGERT, Patrick DAUGHERTY
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Patent number: 12035459Abstract: A method of forming a flexible interconnect circuit is described. The method may comprise laminating a substrate to a conductive layer and patterning the conductive layer using a laser while the conductive layer remains laminated to the substrate thereby forming a first conductive portion and a second conductive portion of the conductive layer. The substrate maintains the orientation of the first conductive portion relative to the second conductive portion during and after patterning. The method may also comprise laminating a first insulator to the conductive layer and removing the substrate from the conductive layer such that the first insulator maintains the orientation of the first conductive portion relative to the second conductive portion while and after the substrate is removed. The method may also comprise laminating a second insulator to the second side of the conductive layer while the first insulator remains laminated to the substrate.Type: GrantFiled: November 28, 2023Date of Patent: July 9, 2024Assignee: CelLink CorporationInventors: Kevin Michael Coakley, Malcolm Parker Brown, Dongao Yang, Michael Lawrence Miller, Paul Henry Lego
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Patent number: 11979976Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.Type: GrantFiled: July 22, 2021Date of Patent: May 7, 2024Assignee: CelLink CorporationInventors: Kevin Michael Coakley, Malcolm Parker Brown, Dongao Yang, Michael Lawrence Miller, Paul Henry Lego
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Publication number: 20240098873Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Applicant: CelLink CorporationInventors: Kevin Michael Coakley, Malcom Parker Brown, Dongao Yang, Michael Lawrence Miller, Paul Henry Lego
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Publication number: 20230414126Abstract: Systems and methods are provided for processing a set of multiple serially acquired magnetic resonance spectroscopy (MRS) free induction decay (FID) frames from a multi-frame MRS acquisition series from a region of interest (ROI) in a subject, and for providing a post-processed MRS spectrum. Processing parameters are dynamically varied while measuring results to determine the optimal post-processed results. Spectral regions opposite water from chemical regions of interest are evaluated and used in at least one processing operation. Frequency shift error is estimated via spectral correlation between free induction decay (FID) frames and a reference spectrum. Multiple groups of FID frames within the acquired set are identified to different phases corresponding with a phase step cycle of the acquisition. Baseline correction is also performed via rank order filter (ROF) estimate and a polynomial fit.Type: ApplicationFiled: March 27, 2023Publication date: December 28, 2023Inventors: James Clayton Peacock, III, John Patrick Claude, Paul Henry Kane, Ricardo Dario Pradenas
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Patent number: 11844601Abstract: An MR Spectroscopy (MRS) system and approach is provided for diagnosing painful and non-painful discs in chronic, severe low back pain patients (DDD-MRS). A DDD-MRS pulse sequence generates and acquires DDD-MRS spectra within intervertebral disc nuclei for later signal processing and diagnostic analysis. An interfacing DDD-MRS signal processor receives output signals of the DDD-MRS spectra acquired and is configured to optimize signal-to-noise ratio by an automated system that selectively conducts optimal channel selection, phase and frequency correction, and frame editing as appropriate for a given acquisition series. A diagnostic processor calculates a diagnostic value for the disc based upon a weighted factor set of criteria that uses MRS data extracted from the acquired and processed MRS spectra for multiple chemicals that have been correlated to painful vs. non-painful discs. A display provides an indication of results for analyzed discs as an overlay onto a MRI image of the lumbar spine.Type: GrantFiled: November 16, 2021Date of Patent: December 19, 2023Assignee: Aclarion, Inc.Inventors: James Clayton Peacock, III, John Patrick Claude, Paul Henry Kane
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Patent number: D1037598Type: GrantFiled: April 21, 2022Date of Patent: July 30, 2024Inventor: Paul Henry Vazquez
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Patent number: D1060661Type: GrantFiled: March 6, 2024Date of Patent: February 4, 2025Assignee: Quip NYC Inc.Inventors: Jonathan Henry Fratti, Eric Glenn Harsh, Steffany V. Tran, Nathan A Herrmann, Simon J. M. Enever, William May, Sean James Wilson, James C. Krause, Maxwell R. Wood-Lee, Paul B. Koh