Abstract: An appliance hub for use in an upper portion of an enclosure can include a substrate configured to be positioned in an upper portion of an enclosure. The appliance hub can include a climate control apparatus mounted on the substrate and the climate control apparatus can be configured to regulate a temperature within the enclosure. The appliance hub can include one or more lighting elements configured to provide light within the enclosure, a plurality of fluid lines connected to the substrate and configured to provide fluid service and return to the climate control apparatus, and/or a plurality of electrical connections connected to the substrate and configured to provide electrical power and/or data to at least one of the climate control apparatus and the one or more lighting elements.

Abstract: An appliance hub for use in an upper portion of an enclosure can include a substrate configured to be positioned in an upper portion of an enclosure. The appliance hub can include a climate control apparatus mounted on the substrate and the climate control apparatus can be configured to regulate a temperature within the enclosure. The appliance hub can include one or more lighting elements configured to provide light within the enclosure, a plurality of fluid lines connected to the substrate and configured to provide fluid service and return to the climate control apparatus, and/or a plurality of electrical connections connected to the substrate and configured to provide electrical power and/or data to at least one of the climate control apparatus and the one or more lighting elements.

Abstract: An appliance hub for use in an upper portion of an enclosure can include a substrate configured to be positioned in an upper portion of an enclosure. The appliance hub can include a climate control apparatus mounted on the substrate and the climate control apparatus can be configured to regulate a temperature within the enclosure. The appliance hub can include one or more lighting elements configured to provide light within the enclosure, a plurality of fluid lines connected to the substrate and configured to provide fluid service and return to the climate control apparatus, and/or a plurality of electrical connections connected to the substrate and configured to provide electrical power and/or data to at least one of the climate control apparatus and the one or more lighting elements.

Abstract: An appliance hub for use in an upper portion of an enclosure can include a substrate configured to be positioned in an upper portion of an enclosure. The appliance hub can include a climate control apparatus mounted on the substrate and the climate control apparatus can be configured to regulate a temperature within the enclosure. The appliance hub can include one or more lighting elements configured to provide light within the enclosure, a plurality of fluid lines connected to the substrate and configured to provide fluid service and return to the climate control apparatus, and/or a plurality of electrical connections connected to the substrate and configured to provide electrical power and/or data to at least one of the climate control apparatus and the one or more lighting elements.

Abstract: An appliance hub for use in an upper portion of an enclosure can include a substrate configured to be positioned in an upper portion of an enclosure. The appliance hub can include a climate control apparatus mounted on the substrate and the climate control apparatus can be configured to regulate a temperature within the enclosure. The appliance hub can include one or more lighting elements configured to provide light within the enclosure, a plurality of fluid lines connected to the substrate and configured to provide fluid service and return to the climate control apparatus, and/or a plurality of electrical connections connected to the substrate and configured to provide electrical power and/or data to at least one of the climate control apparatus and the one or more lighting elements.

Abstract: A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks.

Abstract: An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.

Abstract: An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.

Abstract: A method for converting analog data to digital data includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.

Abstract: A method is disclosed for converting DC power from a first voltage level on an input to a different voltage level on an output for delivery to a load. The method includes switching current in a switching operation from the input to the output through an inductive element and measuring the voltage/current parameters on the input and output. A control algorithm is then utilized to determine control parameters necessary to make a control move to effect the switching operation, the control algorithm utilizing as inputs the measured voltage/current parameters. A digital control system controls the switching operation, which digital control system is operable to be controlled by the control algorithm. Configuration data is received on a serial data bus for configuring the control algorithm. Thereafter, the operation of the control algorithm is modified in response to receiving the configuration information.

Abstract: An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators. The plurality of comparators are programmable to operate in a plurality of operating modes responsive to control bits established in the at least one control register by the processing core.

Abstract: A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks.

Abstract: An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A flash memory stores instructions within the integrated circuit package. A plurality of registers stores data and the program instructions during execution of the program instructions. A JTAG interface provides an interface with the integrated circuit package and enables interactions with the processing core and the plurality of registers. Emulation logic enables manipulating and monitoring program flow through the JTAG interface during execution of the program instructions.

Abstract: An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.

Abstract: Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

Abstract: A method for converting analog data to digital data is disclosed. The method includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.

Abstract: A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.

Abstract: A method is disclosed for converting DC power from a first voltage level on an input to a different voltage level on an output for delivery to a load. The method includes switching current in a switching operation from the input to the output through an inductive element and measuring the voltage/current parameters on the input and output. A control algorithm is then utilized to determine control parameters necessary to make a control move to effect the switching operation, the control algorithm utilizing as inputs the measured voltage/current parameters. A digital control system controls the switching operation, which digital control system is operable to be controlled by the control algorithm. Configuration data is received on a serial data bus for configuring the control algorithm. Thereafter, the operation of the control algorithm is modified in response to receiving the configuration information.

Abstract: Field programmable mixed-signal integrated circuit. A reconfigurable processor system includes a processor core is provided that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core and the functionality associated therewith.

Abstract: A parallel to USB bridge controller includes a USB transceiver for transmitting and receiving on a USB link and a serial interface engine connected to the USB link for converting between USB protocol and serial interface protocol. A memory interface within the controller includes a transmit data register for receiving data from a parallel data link and a receive register for receiving data to be transmitted over the parallel data link. The transmit data register and the receive data register of the memory interface are located within the memory space of a processor connected to the USB serial interface. The memory interface is able to send and receive data between the transmit and receive data registers and an external processor over the parallel data link.