Abstract: An ethernet controller includes analog circuitry for generating a transmit waveform representing transmitted data. A transmit waveform is generated responsive to a digital control signal provided by digital circuitry. The digital control signal is programmable to enable amplification of the transmit waveform.

Abstract: Digital control circuit for switching power supply with pattern generator. A method is disclosed for converting DC power from a first voltage level on an input to a different voltage level on an output for delivery to a load. Current from the input is switched to the output through an inductive element with a plurality of switches, each of the switches driven by a waveform, all of the waveforms driving the switches referenced with a predetermined relationship to a master clock and all operating on a PWM duty cycle of the master clock. The voltage/current parameters on the input and output are measured and then a control algorithm is utilized to determine a change in the PWM duty cycle necessary to make a control move, the control algorithm utilizing as inputs the measured voltage/current parameters. A pre-stored waveform pattern for each of the waveforms is then modified to reflect the change in the PWM duty cycle required for the control move.

Abstract: A single chip network controller for interfacing between a physical network and a processing system on the media side of the network controller. The network controller includes a physical layer for receiving data for transmission to the network and encoding the received data for transmission thereto and for receiving data from the network, and for receiving data from the network and decoding the received data. A media layer is provided for interfacing with the processing system for receiving data from the processing system for interface with the physical layer for encoding and transmission thereof and for receiving decoded data from the physical layer and providing access thereto by the processing system. An on-chip non-volatile memory is provided having a first portion associated with configuration information for configuring the operation of the physical layer and the media layer, and a second portion thereof that is accessible by the processing system on the media side of the network controller.

Abstract: Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

Abstract: Digital control circuit for switching power supply with pattern generator. A method is disclosed for converting DC power from a first voltage level on an input to a different voltage level on an output for delivery to a load. Current from the input is switched to the output through an inductive element with a plurality of switches, each of the switches driven by a waveform, all of the waveforms driving the switches referenced with a predetermined relationship to a master clock and all operating on a PWM duty cycle of the master clock. The voltage/current parameters on the input and output are measured and then a control algorithm is utilized to determine a change in the PWM duty cycle necessary to make a control move, the control algorithm utilizing as inputs the measured voltage/current parameters. A pre-stored waveform pattern for each of the waveforms is then modified to reflect the change in the PWM duty cycle required for the control move.

Abstract: Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein.

Abstract: Method and apparatus for accessing paged memory with indirect addressing. A a method for changing pages of memory in an indirect addressed memory having a plurality of addressable locations therein is diclosed. An index indicative of the page of the memory being addressed is stored in a memory location. The memory is addressed with a direct address that selects one or more of the addressable locations in the addressed page of memory. An interrupt is received from a resource capable of generating an interrupt, which interrupt has associated therewith a defined one of the pages of memory. In response to generation of the interrupt, the value of the stored index t is changed o an index associated with the defined one of the pages of memory associated with the resource. In response to receiving a signal indicative of the generated interrupt having been serviced by a system that services interrupts, the stored index is changed to a different index.

Abstract: Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein.

Abstract: Method and apparatus for accessing paged memory with indirect addressing. A a method for changing pages of memory in an indirect addressed memory having a plurality of addressable locations therein is diclosed. An index indicative of the page of the memory being addressed is stored in a memory location. The memory is addressed with a direct address that selects one or more of the addressable locations in the addressed page of memory. An interrupt is received from a resource capable of generating an interrupt, which interrupt has associated therewith a defined one of the pages of memory. In response to generation of the interrupt, the value of the stored index t is changed o an index associated with the defined one of the pages of memory associated with the resource.