Abstract: This disclosure includes ice packs (10) that comprise paper and absorbent material (22A, 22), and also includes various methods of adding liquid to, freezing, shipping, and/or using such ice packs (10). Some of the ice packs (10) of this disclosure have a body (14) that includes first and second layers (54, 58) of paper and one or more side panels (66A) coupled thereto such that the body (14) is expandable. The absorbent material (22A, 22) of some of the ice packs (10) of this disclosure comprises a laminate having an inner layer (70A, 70B, 70C, 70) of superabsorbent polymer disposed between first and second outer layers (78), where the first outer layer (74) comprises tissue and the second outer layer (78) comprises at least one of a tissue and a carded nonwoven.

Abstract: Efficiently generating selection masks for row selections within indexed address spaces is disclosed. In this regard, in one aspect, an indexed array circuit is provided, comprising a start indicator that indicates a start indexed array row of a row selection, and an end indicator that indicates an end indexed array row of the row selection. The indexed array circuit further comprises a plurality of indexed array rows ordered in a logical sequence, each comprising a row-level compare circuit. Each row-level compare circuit is configured to generate a selection mask indicator based on a first parallel comparison of subsets of bits of a logical address of the indexed array row with corresponding subsets of bits of the start indicator, and a second parallel comparison of subsets of bits of the logical address of the indexed array row with corresponding subsets of bits of the end indicator.

Abstract: Multiple-hot (multi-hot) bit decoding in a memory system for activating multiple memory locations in a memory for a memory access operation are disclosed. In one aspect, a multi-hot bit decoding system is provided that includes a memory access control system that includes a decoder. The decoder is configured to decode an address for a memory access operation into a single-hot bit decode word for activating a memory row at the encoded address. To automatically access another memory row(s) for a memory access operation, the memory access control system also includes a mapping circuit configured to provide an additional decode word(s) for activating another memory row(s) based on the address. The decode word and additional decode word(s) are merged to provide a multi-hot bit decode word that is asserted onto a decode wordline such that multiple memory rows are activated for a memory access operation.

Abstract: Systems and methods relate to memory operations in a memory array. A compare operation is performed using a sense amplifier. True and complement versions of a search bit are compared with true and complement versions of a data bit stored in a data row of the memory array to generate true and complement sense amplifier inputs. The true and complement sense amplifier inputs are amplified in the sense amplifier to generate a single-ended match signal. The single-ended match signal can be aggregated with other single-ended match signals in the data row to determine whether there is a hit or miss for a compare operation on the entire data row.

Abstract: A method and apparatus for reading bitcell data stored in a content addressable memory (CAM) includes controlling a first compare line of a first column of an array of bitcells to a first logic state while controlling a second compare line of the first column as well as first and second compare lines of each of the other columns of the array to a second logic state during a second mode of operation, in order to provide the bitcell data stored in at least one bitcell of the first column to a respective match line. The method also includes reading the bitcell data on the respective match line.

Abstract: Efficiently generating selection masks for row selections within indexed address spaces is disclosed. In this regard, in one aspect, an indexed array circuit is provided, comprising a start indicator that indicates a start indexed array row of a row selection, and an end indicator that indicates an end indexed array row of the row selection. The indexed array circuit further comprises a plurality of indexed array rows ordered in a logical sequence, each comprising a row-level compare circuit. Each row-level compare circuit is configured to generate a selection mask indicator based on a first parallel comparison of subsets of bits of a logical address of the indexed array row with corresponding subsets of bits of the start indicator, and a second parallel comparison of subsets of bits of the logical address of the indexed array row with corresponding subsets of bits of the end indicator.

Abstract: Multiple-hot (multi-hot) bit decoding in a memory system for activating multiple memory locations in a memory for a memory access operation are disclosed. In one aspect, a multi-hot bit decoding system is provided that includes a memory access control system that includes a decoder. The decoder is configured to decode an address for a memory access operation into a single-hot bit decode word for activating a memory row at the encoded address. To automatically access another memory row(s) for a memory access operation, the memory access control system also includes a mapping circuit configured to provide an additional decode word(s) for activating another memory row(s) based on the address. The decode word and additional decode word(s) are merged to provide a multi-hot bit decode word that is asserted onto a decode wordline such that multiple memory rows are activated for a memory access operation.

Abstract: In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read wordline from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.

Abstract: Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.

Abstract: Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.

Abstract: A method and apparatus to produce controlled ablation of material through the use of laser pulses of short pulse widths at short wavelengths.

Abstract: The hybrid dynamic-static encoder described herein may combine dynamic and static structural and logical design features that strategically partition dynamic nets and logic to substantially eliminate redundancy and thereby provide area, power, and leakage savings relative to a fully dynamic encoder with an equivalent logic delay. For example, the hybrid dynamic-static encoder may include identical top and bottom halves, which may be combined to produce final encoded index, hit, and multi-hit outputs. Each encoder half may use a dynamic net for each index bit with rows that match a search key dotted. If a row has been dotted to indicate that the row matches the search key, the dynamic nets associated therewith may be evaluated to reflect the index associated with the row. Accordingly, the hybrid dynamic-static encoder may have a reduced set of smaller dynamic nets that leverage redundant pull-down structures across the index, hit, and multi-hit dynamic nets.

Abstract: Systems and methods for detecting and suppressing crowbar currents in memory arrays. A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (SRAM) array having cross-coupled bitline keepers. When a simultaneous read and write operation to a first entry of the memory array is detected, the read operation to the first entry is suppressed and a dummy read operation to a second entry of the memory array is performed. The write operation to the first entry is allowed to proceed undisturbed.

Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.

Abstract: The method and apparatus to fabricate vias in the gallium nitride (“GaN”) layer of a GaN monolithic microwave integrated circuit (“MMIC”). The method and apparatus create vias in the GaN layer of a GaN MMIC through the use of controlled laser ablation and spectroscopic analysis of SiC and CVD diamond MMICs. The use of spectroscopic measurements helps to control the ablation by detecting a change in layers, including the GaN layer. The method and apparatus uses short pulse length, short wavelength, and a lower threshold intensity to remove material without undue heating or damage to the surrounding areas while retaining depth control.

Abstract: Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.

Abstract: The hybrid dynamic-static encoder described herein may combine dynamic and static structural and logical design features that strategically partition dynamic nets and logic to substantially eliminate redundancy and thereby provide area, power, and leakage savings relative to a fully dynamic encoder with an equivalent logic delay. For example, the hybrid dynamic-static encoder may include identical top and bottom halves, which may be combined to produce final encoded index, hit, and multi-hit outputs. Each encoder half may use a dynamic net for each index bit with rows that match a search key dotted. If a row has been dotted to indicate that the row matches the search key, the dynamic nets associated therewith may be evaluated to reflect the index associated with the row. Accordingly, the hybrid dynamic-static encoder may have a reduced set of smaller dynamic nets that leverage redundant pull-down structures across the index, hit, and multi-hit dynamic nets.

Abstract: Systems and methods for detecting and suppressing crowbar currents in memory arrays. A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (SRAM) array having cross-coupled bitline keepers. When a simultaneous read and write operation to a first entry of the memory array is detected, the read operation to the first entry is suppressed and a dummy read operation to a second entry of the memory array is performed. The write operation to the first entry is allowed to proceed undisturbed.

Abstract: Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.

Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.