Abstract: A latch integrated circuit has synchronous data loading and self-timed asynchronous data capture characteristics. The integrated circuit may include a latch, a pulse generator and a comparator. The latch can be responsive to a data signal and a write enable signal. The pulse generator may be configured to generate the write enable signal as a pulse. This pulse may have a leading edge synchronized with a first edge of a clock signal and a self-timed trailing edge synchronized with an edge of a comparison signal. The comparator may be configured to generate the comparison signal in response to comparing logic levels of at least two nodes within the integrated circuit.

Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.

Abstract: Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.

Abstract: Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.

Abstract: A latch integrated circuit has synchronous data loading and self-timed asynchronous data capture characteristics. The integrated circuit may include a latch, a pulse generator and a comparator. The latch can be responsive to a data signal and a write enable signal. The pulse generator may be configured to generate the write enable signal as a pulse. This pulse may have a leading edge synchronized with a first edge of a clock signal and a self-timed trailing edge synchronized with an edge of a comparison signal. The comparator may be configured to generate the comparison signal in response to comparing logic levels of at least two nodes within the integrated circuit.

Abstract: A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.

Abstract: A method and apparatus to produce controlled ablation of material through the use of laser pulses of short pulse widths at short wavelengths.

Abstract: A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.

Abstract: A safe, reliable and rapid system for the detection of nuclear materials within containers includes the use of pulsed high-intensity gamma rays that can penetrate a container and its contents and can be detected outside the container to provide a display in which high-Z material, including lead, uranium, plutonium and other nuclear substances that absorb gamma rays are detected as black regions on the display. In one embodiment, orthogonal pulsed gamma ray beams illuminate the container from two different directions to provide three-dimensional slices from which the existence and location of nuclear threat materials can be ascertained in as little as four seconds for a 40-foot container.

Abstract: Disclosed is a single-cast, thin wall structure capable of withstanding impinging gases at temperatures of 4300° F. and higher, and method of making the same.

Abstract: A single-cast, thin wall structure capable of withstanding impinging gases at temperatures of 4300.degree. F. and higher, and method of making the same.

Abstract: The present invention relates to a method and apparatus for producing a cast structure. In one embodiment of the present invention an alloy casting mold has molten alloy injected therein to facilitate completely filling a part cavity within the mold. Further, an alloy charge pressure control device is utilized to reduce the charge pressure of the molten alloy during its injection into the mold cavity to minimize distortion and creep of the ceramic shell. In one form of the present invention the charge pressure control device removes excess alloy so as to reduce the head pressure of the molten alloy thereby eliminating the undesirable creep of the ceramic shell.