Patents by Inventor Paul J. Broyles

Paul J. Broyles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070283003
    Abstract: There is provided a system and a method for provisioning a computer system. More specifically, in accordance with one embodiment, there is provided a computer system configured to generate provisioning information for the computer system, wherein the provisioning information includes a product identifier and a passphrase, and upload the provisioning information into a remote access system for the computer system.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 6, 2007
    Inventors: Paul J. Broyles, Mark A. Piwonka
  • Patent number: 7076643
    Abstract: Systems and methods are disclosed for detecting and reporting revision identification numbers (“rev IDs”). When the revision identifier of hardware that the computer is built out of changes, this can impact the actual and/or perceived stability of the computer. In some embodiments, devices may include a programmable register, which may be programmed to a revision identifier. This number may be the revision identifier of a previous version of this hardware that was originally incorporated in the system design.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: July 11, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Paul J. Broyles, III
  • Patent number: 6873333
    Abstract: A computer system has a selectable set-up feature to adjust the display screen image presented during power on self test, or POST. The computer memory contains two sets of information that can be presented on the video display screen. An application of power to the computer system, a first form of information from a first video memory area is normally presented to the computer output device. This information is simpler in format, requiring less memory. Also, upon the application of power to the computer system, flags or semaphores direct substantially all of a detailed or verbose screen information from initialization, configuration, or other boot-time routines to a second video memory area while information in the first video memory area is presented on the display. Upon receiving one of a predetermined set of commands, the computer system switches from the first display to the second display, presenting the second verbose screen information on the video screen.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: March 29, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Rahul G. Patel, Paul J. Broyles
  • Patent number: 6832320
    Abstract: An “ownership tag” in a special area of memory of a computer system identifies an owner of the computer system by displaying the ownership tag during initialization of the computer system. The ownership tag may be presented during the installation and execution of the Basic Input Output System (BIOS) preferably during Power on Self Test (POST) process. An administrator may access the ownership tag by interrupting the process by pressing the an appropriate key, which transitions the computer to an administrator set up mode. An administrator able to enter the administrator password may then alter the contents of the protected memory, changing the ownership tag. The ownership tag is preferably stored in a region of memory not accessible to a typical user, but accessible to an administrator aware of the administrator password. The ownership tag is stored in a flash memory, which is very difficult to remove from the system board, or to modify without administrator-level security access.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: December 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paul J. Broyles, III, Rahul G. Patel, Mark A. Piwonka
  • Publication number: 20040148499
    Abstract: Systems and methods are disclosed for detecting and reporting revision identification numbers (“rev IDs”). When the revision identifier of hardware that the computer is built out of changes, this can impact the actual and/or perceived stability of the computer. In some embodiments, devices may include a programmable register, which may be programmed to a revision identifier. This number may be the revision identifier of a previous version of this hardware that was originally incorporated in the system design.
    Type: Application
    Filed: January 28, 2003
    Publication date: July 29, 2004
    Inventor: Paul J. Broyles
  • Patent number: 6467038
    Abstract: A computer system that includes a system ROM with at least two sets of character strings, one set in English and at least one other set in a non-English language. Generally, each set of character strings includes characters, words and phrases that are translations of corresponding character strings in the other sets. In a preferred embodiment, the system ROM includes only two sets of character strings—one English and the other non-English. The non-English set of character strings is included as part of a “language module” stored or flashed into the system ROM. The character strings preferably are used to provide information and instructions to a user during system setup. When setup is run, the computer system determines whether a valid international language module is included in the system ROM. If a valid language module is included, the user is prompted to select either English or whatever international language is provided in the language module.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: October 15, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Mark A. Piwonka, Paul J. Broyles, III, Patrick L. Gibbons
  • Patent number: 6405311
    Abstract: A computer system contains a revision indicator which is stored in a protected special area of computer memory. The revision indicator specifies the revision of the hardware actually present in the system. The revision indicator data is presented by the computer during power up so that a user may be aware of the type and configuration of the computer system hardware. The revision indicator may be displayed by the computer system BIOS during power on self test (POST), for example. The memory storing the revision indicator is protected from erroneous or unauthorized change.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: June 11, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Paul J. Broyles, Mark A. Piwonka, Daniel G. Parsons
  • Patent number: 6356965
    Abstract: A computer system is provided with a dynamically reconfigurable boot order. In one embodiment, the computer comprises a user input device, a nonvolatile memory, a network interface, a boot trigger, and a CPU. The CPU is coupled to the user input device to detect a predetermined key press, coupled to the boot trigger to detect the assertion of a system reset signal, and coupled to the nonvolatile memory to retrieve a system BIOS in response to assertion of the system reset signal. The CPU executes the BIOS to initialize the computer system, and as part of the system initialization, the CPU determines a first target boot-up device. Preferably if the predetermined key has been pressed during the system initialization, the CPU alters the default boot order to select the network interface as the first target boot up device. The network interface is configurable to retrieve an operating system from a network device for the CPU to execute.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: March 12, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Paul J. Broyles, Don R. James, Jr.
  • Patent number: 6243809
    Abstract: A computer system provides for flashing a non-volatile memory image to a non-volatile memory and reading data from a non-volatile memory independently of an operating system. An image buffer is allocated in a volatile memory of the computer system. If flashing a non-volatile memory image to the non-volatile memory is desired, the image buffer is loaded with a portion of the non-volatile memory image. BIOS interface code is then called to place an SMI event code into a memory and to generate a system management interrupt causing the computer system to enter a system management mode. SMI handler code examines the SMI event code and calls SMI service code. Next, the image buffer is located and the portion of the non-volatile memory in the image buffer is flashed to the non-volatile memory by the SMI service code. Locating the image buffer may include locating an image header defined within the volatile memory. The image header may include a password for providing access to the non-volatile memory.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: June 5, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Patrick L. Gibbons, Paul J. Broyles, III
  • Patent number: 5978913
    Abstract: A fast boot computer which has three user-selectable modes of performing POST operations. The user can select full POST or quick POST be performed, as in conventional computers. However, he can also select an intermediate mode, wherein the full POST is performed if and only if a given number of days (as programmed by the user) have elapsed since the last full POST operation. This permits users to set their own trade-off between fast boot operation and maximum reliability.
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: November 2, 1999
    Assignee: Compaq Computer Corporation
    Inventors: Paul J. Broyles, Mark A. Piwonka, Cuong V. Nguyen
  • Patent number: 5974501
    Abstract: A memory controller and method of operation for detecting different type of dynamic random access memory (DRAM) devices in a computer system. The memory controller has capabilities for improved page hits which cause the row address strobe signals to remain asserted following certain cycles. A mechanism in the memory controller selectably disables column address strobing. Different DRAM types are distinguishable by reading back data previously written to a memory location. Data is written to memory with a cycle causing the memory controller to keep the row address strobes asserted. Column address strobing is disabled. A read back cycle is performed without column address strobing. If data is present, the DRAM is an extended data output (EDO) DRAM. If data is not present, the DRAM is a fast page mode DRAM.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: October 26, 1999
    Assignee: Compaq Computer Corporation
    Inventors: Charles N. Shaver, Timothy R. Zinsky, Paul J. Broyles, John E. Larson