Abstract: A console concentrator is provided as an integral part of a modular computer system to provide access to consoles in the components of the system in a secure and flexible manner. For example, the console concentrator can provide a common point of access to respective consoles of a plurality of blades in blade server system. It can also provide access to consoles of, for example, a switch processor in the blade server system.

Abstract: In a modular computer system comprising at least one information processing module removably received at a first face of a housing, at least one computer support module removably received at a second face of the housing, and at least one power supply module removably received at the second face of the housing, a connections member is provided. The connections member comprises at least one connector at a first face of the member arranged to connect to a connector of the at least one information processing module. The connections member further comprises at least one connector at a second face of the member arranged to connect to a connector of the at least one computer support module. The connections member also comprises at least one connector at the second face of the member arranged to connect to a connector of the at least one power supply module.

Abstract: A power sub-system controls the supply of power to a field replaceable unit. The power sub-system includes a main power controller that supplies main power to at least a first component of the field replaceable unit, and a standby power controller that supplies standby power to at least a second component of the field replaceable unit. The main power controller is operable to switch off the supply of main power to a first component in response to the detection of a fault, whereas the standby power controller maintains the supply of standby power to the second component. By providing separates power controllers for main and standby power, it is possible to maintain power to one or more selected components of the FRU in the event of a fault that requires main power to the FRU to be cut. Standby power is switched off automatically in response to a first change in state of an interlock signal that is indicative of the field replaceable unit being released.

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is operable to permit direct memory access to memory of the processing sets by a device on the device bus, to arbitrate between the first and the second processing sets for access to the bridge in a first, split, mode, and to monitor lockstep operation of the first and second processing sets in a second, combined, mode. The dirty RAM mechanism defines a dirty indicator (e.g., a bit) for each of a plurality of regions of processing set memory, a dirty indicator being set to a predetermined value when the region of memory has been written to by a DMA access.

Abstract: A bridge for a multi-processor system provides interfaces to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism arbitrates between the first and the second processing sets for access to each others I/O bus and to the device bus in a first, split, mode, and monitors lockstep operation of the first and second processing sets in a second, combined, mode. On detecting a lockstep error in the combined mode, the bridge transfers to an error mode. The bridge control mechanism buffers write accesses in a posted write buffer in the error mode pending resolution of the error.

Abstract: A bridge for a computer system comprising at least a first processing set and a second processing set each connected to the bridge via an I/O bus. A resource control mechanism in the bridge comprises: an interface for exchanging signals with one or more resource slots of a device bus that is capable of being connected to the bridge, each of the resource slots being capable of communicating with a system resource; and a register associated with each system resource, the register having switchable indicia that indicate an operating state of the associated system resource, the control mechanism being operable in use to direct signals to and/or from respective system resources of the computer system.

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. The bridge also includes a memory subsystem and a bridge control mechanism. The bridge control mechanism is operable to monitor operation of the first and second processing sets in a combined, lockstep, operating mode and to be responsive to detection of a lockstep error to cause the bridge to be operable in an error mode in which write accesses initiated by the processor sets are buffered in a bridge buffer pending resolution of the error mode. A respective buffer region is provided for each processing set. In an initial error mode, any complete device write accesses initiated by the processing sets are stored in a posted write buffer. Where data is in transit through the bridge on entry to the error mode, the data is diverted to one or more disconnect registers.

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is operable to compare address and data phases of I/O accesses by the first and second processing sets. A direct memory access mechanism is operable to initiate a direct memory access operation to read from a corresponding location in each processor set into a respective dissimilar data register associated with each processing set. The bridge control mechanism is operable during the direct memory access operation to disregard differences in the data phase for the dissimilar data write access. As a result it is possible to transfer dissimilar data from the processors into the bridge in a combined (lockstep comparison) mode.

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is configured to compare address and data phases of I/O accesses by the first and second processing sets. At least one dissimilar data register is provided for each processing set. The bridge control mechanism is operable in response to an address phase of a dissimilar data register write access to disregard any differences in the data phase for the dissimilar data write access. Non-deterministic data (for example relating to a real time clock) can be output from the processing sets in a combined (lockstep comparison) mode. A read destination address supplied in common by the first and second processing sets for a dissimilar data read access can cause data read from a determined one of the dissimilar data registers to be supplied the first and second processing sets.

Abstract: A processing system includes a mechanical support structure and a number of processing modules. Each processing module includes a module connector for mounting the processing module with respect to the support structure and at least one optical transceiver for providing an optical data link between the processing module and a further processing module mounted with respect to the mechanical support structure.

Abstract: A bus controller for a computer system. The controller comprises a monitor for monitoring request signals and response signals between a first component and a second component each connected to a bus of the computer system; and a terminator controlled by the monitor to terminate a request from one of the first and second components if a response to the request has not issued within a predetermined period of time.