Patents by Inventor Paul J. Griffiths
Paul J. Griffiths has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11952579Abstract: A recombinant DNA construct is disclosed. When the recombinant DNA construct is expressed in a plant or a plant cell, endogenous HD-Zip class II proteins become less able to repress DNA transcription of the genes they typically regulate. The recombinant DNA construct can be expressed in plant cells to produce plants with enhanced phenotypes. Methods of making transgenic plants comprising the recombinant DNA construct, and plants produced thereby are also disclosed.Type: GrantFiled: October 15, 2020Date of Patent: April 9, 2024Assignee: Monsanto Technology LLCInventors: Cara L. Griffith, Abha Khandelwal, Paul J. Loida, Elena A. Rice, Rebecca L. Thompson, Sivalinganna Manjunath
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Publication number: 20240093221Abstract: This disclosure provides recombinant DNA constructs and transgenic plants having enhanced traits such as increased yield, increased nitrogen use efficiency, and enhanced drought tolerance or water use efficiency. Transgenic plants may include field crops as well as plant propagules and progeny of such transgenic plants. Methods of making and using such transgenic plants are also provided. This disclosure also provides methods of producing seed from such transgenic plants, growing such seed, and selecting progeny plants with enhanced traits. Also disclosed are transgenic plants with altered phenotypes which are useful for screening and selecting transgenic events for the desired enhanced trait.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Inventors: Edwards M. Allen, Bettina Darveaux, Stephen M. Duff, Mary Fernandes, Barry S. Goldman, Cara L. Griffith, Balasulojini Karunanandaa, Saritha V. Kuriakose, Paul J. Loida, Linda L. Lutfiyya, Robert J. Meister, Monnanda S. Rajani, Dhanalakshmi Ramachandra, Elena A. Rice, Daniel Ruzicka, Anagha M. Sant, Jon J. Schmuke, Rebecca L. Thompson, Srikanth Babu Venkatachalayya, Tyamagondlu V. Venkatesh, Huai Wang, Xiao Yang, Qin Zeng, Jianmin Zhao
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Patent number: 11452873Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).Type: GrantFiled: June 17, 2020Date of Patent: September 27, 2022Assignee: Boston Scientific Neuromodulation CorporationInventors: Jordi Parramon, David K. L. Peterson, Paul J. Griffith
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Publication number: 20220088392Abstract: A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.Type: ApplicationFiled: December 2, 2021Publication date: March 24, 2022Inventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
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Patent number: 11207521Abstract: A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.Type: GrantFiled: June 17, 2019Date of Patent: December 28, 2021Assignee: Boston Scientific Neuromodulation CorporationInventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
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Publication number: 20200316381Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).Type: ApplicationFiled: June 17, 2020Publication date: October 8, 2020Inventors: Jordi Parramon, David K.L. Peterson, Paul J. Griffith
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Patent number: 10744325Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).Type: GrantFiled: February 23, 2018Date of Patent: August 18, 2020Assignee: Boston Scientific Neuromodulation CorporationInventors: Jordi Parramon, David K. L. Peterson, Paul J. Griffith
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Publication number: 20190299007Abstract: A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.Type: ApplicationFiled: June 17, 2019Publication date: October 3, 2019Inventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
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Patent number: 10391322Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.Type: GrantFiled: February 14, 2018Date of Patent: August 27, 2019Assignee: Boston Scientific Neuromodulation CorporationInventors: Paul J. Griffith, Goran N. Marnfeldt, Jordi Parramon
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Patent number: 10363422Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.Type: GrantFiled: April 19, 2017Date of Patent: July 30, 2019Assignee: Boston Scientific Neuromodulation CorporationInventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
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Publication number: 20180178012Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).Type: ApplicationFiled: February 23, 2018Publication date: June 28, 2018Inventors: Jordi Parramon, David K.L. Peterson, Paul J. Griffith
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Publication number: 20180169424Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.Type: ApplicationFiled: February 14, 2018Publication date: June 21, 2018Inventors: Paul J. Griffith, Goran N. Marnfeldt, Jordi Parramon
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Patent number: 9956411Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).Type: GrantFiled: April 6, 2016Date of Patent: May 1, 2018Assignee: Boston Scientific Neuromodulation CorporationInventors: Jordi Parramon, David K. L. Peterson, Paul J. Griffith
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Patent number: 9925385Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.Type: GrantFiled: October 10, 2016Date of Patent: March 27, 2018Assignee: Boston Scientific Neuromodulation CorporationInventors: Paul J. Griffith, Goran N. Marnfeldt, Jordi Parramon
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Patent number: 9795793Abstract: Architectures for an implantable neurostimulator system having a plurality of electrode-driver integrated circuits (ICs) in provided. Electrodes from either or both ICs can be chosen to provide stimulation, and one of the IC acts as the master while the other acts as the slave. A parallel bus operating in accordance with a communication protocol couples the ICs, and certain functional blocks not needed in the slave are disabled. Stimulation parameters are loaded via the bus into each IC, and a stimulation enable command is issued on the bus to ensure simultaneous stimulation from the electrodes on both ICs. Clocking strategies are also disclosed to allow clocking of the master and slave ICs to be independently controlled, and to ensure that relevant internal and bus clocks used in the system are synchronized.Type: GrantFiled: October 5, 2011Date of Patent: October 24, 2017Assignee: Boston Scientific Neuromodulation CorporationInventors: Jordi Parramon, Emanuel Feldman, Paul J. Griffith, Jess W. Shi
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Publication number: 20170216600Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.Type: ApplicationFiled: April 19, 2017Publication date: August 3, 2017Inventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
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Patent number: 9656081Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.Type: GrantFiled: March 7, 2016Date of Patent: May 23, 2017Assignee: Boston Scientific Neuromodulation CorporationInventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
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Publication number: 20170021181Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.Type: ApplicationFiled: October 10, 2016Publication date: January 26, 2017Inventors: Paul J. Griffith, Goran N. Marnfeldt, Jordi Parramon
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Patent number: 9468771Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.Type: GrantFiled: September 18, 2015Date of Patent: October 18, 2016Assignee: Boston Scientific Neuromodulation CorporationInventors: Paul J. Griffith, Goran N. Marnfeldt, Jordi Parramon
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Publication number: 20160213929Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).Type: ApplicationFiled: April 6, 2016Publication date: July 28, 2016Inventors: Jordi Parramon, David K.L. Peterson, Paul J. Griffith