Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).

Abstract: An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a signal integrated circuit (IC). Each of the functional blocks communicates with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG.

Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.

Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.

Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.

Abstract: Disclosed herein are current output architectures for implantable stimulator devices. Current source and sink circuitry is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking an amount of current to or from any one of the electrodes of the device. The current source circuitry is distinct from the current sink circuitry, and the two share no common circuit nodes prior to connection to the electrodes. In other words, the current source circuitry and the current sink circuitry do not share a common node other than the electrodes. Each stage is preferably formed of a current mirror for receiving a reference current and outputting a scaled version of current to that stage's switch bank. The scalar at each stage can be set by wiring a desired number of output transistors in parallel.

Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.

Abstract: Disclosed herein are current output architectures for implantable stimulator devices. Current source and sink circuitry is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking an amount of current to or from any one of the electrodes of the device. The current source circuitry is distinct from the current sink circuitry, and the two share no common circuit nodes prior to connection to the electrodes. In other words, the current source circuitry and the current sink circuitry do not share a common node other than the electrodes. Each stage is preferably formed of a current mirror for receiving a reference current and outputting a scaled version of current to that stage's switch bank. The scalar at each stage can be set by wiring a desired number of output transistors in parallel.

Abstract: Disclosed herein is a current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG). Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide a coarse and fine current resolution to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).

Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).

Abstract: An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a signal integrated circuit (IC). Each of the functional blocks communicate with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG without the need for a major redesign of the main IPG IC.

Abstract: Disclosed herein is a current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG). Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide a coarse and fine current resolution to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).

Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.

Abstract: Architectures for an implantable neurostimulator system having a plurality of electrode-driver integrated circuits (ICs) in provided. Electrodes from either or both ICs can be chosen to provide stimulation, and one of the IC acts as the master while the other acts as the slave. A parallel bus operating in accordance with a communication protocol couples the ICs, and certain functional blocks not needed in the slave are disabled. Stimulation parameters are loaded via the bus into each IC, and a stimulation enable command is issued on the bus to ensure simultaneous stimulation from the electrodes on both ICs. Clocking strategies are also disclosed to allow clocking of the master and slave ICs to be independently controlled, and to ensure that relevant internal and bus clocks used in the system are synchronized.

Abstract: An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a signal integrated circuit (IC). Each of the functional blocks communicate with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG without the need for a major redesign of the main IPG IC.

Abstract: Disclosed herein is a current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG). Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide a coarse and fine current resolution to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).

Abstract: An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a signal integrated circuit (IC). Each of the functional blocks communicate with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG without the need for a major redesign of the main IPG IC.

Abstract: An air suspension system includes an air spring having an air cell and a piston. Preferably, the air cell tightly conforms to the piston and has a frustro-conical tapered configuration. By providing a tight conformal fit between the piston and the air cell, and by expanding the diameter of the air cell therefrom, the likelihood that the air cell will invert is substantially decreased. Similarly, when the air cell is deflated the taper facilitates the air cell obtaining the original rolled or deflated position. In another embodiment, the damper slows the extension of the longitudinal member to provide more time for an anti-vacuum system to equalize the pressure within the air cell.

Abstract: A suspension system includes a longitudinal member, an air spring, a damper and an axle assembly. The air spring is not directly attached to the chassis but is mounted to contact a locating plate attached to the chassis. The locating plate includes a lip such that the locating plate is of a frustum configuration that laterally locates and self aligns the air spring upon pivotal movement and re-alignment of the air spring with the chassis. Preferably, the suspension system includes a protective skirt which aids in bringing the air cell into a correct position with the locating plate. In addition the axle assembly extends away from the chassis at a speed restricted by the damper such that the anti-vacuum system can equalize the pressure within the air cell.