Abstract: A method of nondestructively monitoring filled or unfilled via and trench profiles during the manufacture of semiconductor devices. A selected filled or unfilled via or trench is scanned with overlapped excitation pulses that form a temporally varying excitation radiation field causing a time-dependent ripple to be generated that is irradiated by a probe pulse that diffracts into at least two signal beams. One of the diffracted signal beams is detected and digitized to produce a digitized waveform signal that is analyzed in a CPU to obtain a frequency of the digitized waveform signal and is compared to characterization waveforms stored in a database to determine the profile of the selected filled or unfilled via or trench.

Abstract: A method of determining an accurate disposition decision for each inspected layer in a wafer lot wherein a measured defect density is compared to a calculated disposition criterion determined for each inspected layer. If the measured defect density is above the calculated disposition criterion the wafer lot is placed on hold and if the measured defect density is at or below the calculated disposition criterion the wafer lot is sent to the next process. The disposition criterion for each layer is determined from a yield value determined for each layer. The yield value is the yield necessary for each layer to obtain a profitable product and is determined from cost data for each die in the wafer lot and a risk factor determined by management and includes market data such as selling price and demand for the product. The yield value is combined with defect sensitivity determined for each layer. The defect sensitivity is determined from the combination of critical area and historical frequency for each layer.

Abstract: A method of manufacturing semiconductor devices wherein images of non-defect anomalies are captured and stored with image data and linkage data in a database. The non-defect anomaly data is stored in database for later retrieval.

Abstract: A method of manufacturing a semiconductor wafer wherein each layer to be scanned is scanned in a scan tool after determination of whether the current recipe is contained in the scan tool. The recipe in the scan tool is compared to the current recipe stored in a server. If the recipe in the scan tool is not the current recipe the current recipe is loaded into the scan tool from the server. The recipes in the server are updated from associated scan tools.

Abstract: A method of manufacturing semiconductor wafers using a simulation tool to determine a set of predicted wafer electrical test parameters. The set of predicted wafer electrical test parameters are compared with wafer electrical test specifications tabulated for each process during the manufacturing process. During the comparison, it is determined whether the predicted wafer electrical test parameters are within the specifications for the process and circuit simulations are then conducted using the predicted wafer electrical test parameters. Device performance is predicted from the circuit simulations and the disposition of the wafer lot is determined utilizing tabulated from a disposition performance table.

Abstract: A method of manufacturing a semiconductor device with dual damascene structures. A first and second layer of interlayer dielectric separated by a first layer of etch stop material is formed on the surface of a semiconductor substrate on and in which active devices have been formed. A second layer of an etch stop material is formed on the surface of the second layer of interlayer dielectric. A layer of photoresist is formed on the second layer of etch stop material and is patterned and etched to expose portions of the second etch stop material. The exposed portions of the second etch stop material are anisotropically etched exposing portions of the second layer of interlayer dielectric. The exposed portions of the second layer of interlayer dielectric are first anisotropically etched and then isotropically etched. The etch stop layer between the first and second interlayer dielectric is anisotropically etched and the first layer of interlayer dielectric is anisotropically etched.

Abstract: A method of manufacturing a semiconductor device having multiple layers of interconnects that are filled in a single conductive material filling step. Two layers of interlayer dielectric separated by an etch stop layer are formed over a layer including metal structures in contact with electrodes of active devices formed in and on a semiconductor substrate. A layer of photoresist is formed on a second etch stop layer formed on the upper layer of interlayer dielectric. The layer of photoresist is patterned and etched. Masking and etching processes form openings in the first and second layers of interlayer dielectric including openings to the metal structures. The openings are filled in a single conductive material filling step.

Abstract: A method of manufacturing semiconductor devices wherein a partially completed semiconductor device having a first and second layer of interlayer dielectric and a first and second etch stop layer has the second etch stop layer masked and etched with an etch pattern having dimensions of the trench structure to be formed in the second interlayer dielectric. The second layer dielectric and first etch stop layer are then masked and etched with an etch pattern having dimensions of the via structure to be formed in the first interlayer dielectric. The remaining portions of the photoresist is removed and exposed portions of the second layer of interlayer dielectric and the first layer of interlayer dielectric are then etched simultaneously. The via structure and trench structure are then simultaneously filled with a conductive material.

Abstract: A multiple chip hybrid package using bump technology having multiple chips electrically connected using a flip chip technology such as solder bump technology. Portion of at least one chip is electrically connected to electrical leads connecting terminals inside the package to pins outside the package.

Abstract: A method of utilizing associated process data parameters in the manufacture of semiconductor wafers by converting tool-based data to lot based data in order to predict wafer electrical test results from measured in-line critical dimensions, lot based data and the converted tool-based data. The converted tool-based data is obtained by interpolating data between a measurement obtained from a tool at a first time and a measurement obtained from the tool at a second time. The data association is obtained using LaPlace-Everett interpolation. The converted tool-based data can also be obtained by extrapolating data from the historical measurements taken from the tool.

Abstract: A method of filling trenches in a semiconductor wafer with a conductive material is disclosed by selectively electroplating the semiconductor wafer. The trenches are lined with a barrier layer and a seed layer and the semiconductor wafer is submerged in a solution having ions of the selected conductive material. An electrical potential is applied to the electroplating solution and the semiconductor wafer. The seed layer in the trench causes the conductive material ions to be plated in the trench.

Abstract: A multichip integrated semiconductor device having a portion of a first chip bonded to electrical leads in a package using a flip chip technology such as solder bump technology and a second chip bonded to a second portion of the first chip using a flip chip technology such as solder bump technology.

Abstract: A method of using universal alignment marks on a semiconductor wafer that allows the accurate alignment of scanning and analysis tools in relation to the semiconductor wafer. The information in the universal alignment marks are utilized by a vendor generated algorithm incorporated into the respective scanning or analysis tools to accurately position the tool in relation to the semiconductor wafer.

Abstract: A method of identifying individual semiconductor devices with a unique inscription during the manufacturing process for the semiconductor devices. Each individual semiconductor device is marked during a final lithographic stepping exposure with a direct write laser mounted either in the stepper in the lithographic system working concurrently with the stepping fields during the final metal layer lithographic stepping exposure or during a post stepping pre-development treatment. The marking on the devices includes device identification, lot number and die number.

Abstract: A method of manufacturing semiconductor wafers using a simulation tool to determine a set of predicted wafer electrical test measurements that are compared to a set of target wafer electrical test measurements to obtain a set of optimized process parameters for the equipment for the next process. The optimized process parameters are compared to the equipment characteristics for the equipment of the next process and the process parameters for the next process are automatically adjusted.

Abstract: A defect management system with a method to update a database with defect data concerning propagator defect data. Defect data obtained from each layer formed on a semiconductor wafer is stored in a relational database. Defect data determined in a current layer to be defect data for a defect observed in a previous layer is defined as data concerning a propagator defect. Propagator defect data is used to update the data in the database relating to the previous layer.

Abstract: A method of manufacturing a semiconductor device with multiple dual damascene structures that maintains the maximum density. A first dual damascene structure having a first via and a first trench is formed in a first interlayer dielectric and a first etch stop layer formed on the planarized surface of the first interlayer dielectric. Two layers of interlayer dielectric separated by a second etch stop layer is formed on the surface of the first etch stop layer. A third etch stop layer is formed on the upper layer of interlayer dielectric and a first photoresist layer formed on the third etch stop layer. The photoresist layer is etched having a dimension coinciding with a width dimension of the first via. The third etch stop layer is selectively etched and the first photoresist layer removed and replaced by a second photoresist layer. The second photoresist layer is etched having a dimension coinciding with a width dimension of the first trench.

Abstract: A method of manufacturing a semiconductor device including a step of filling crevices or non-level regions formed during the manufacture of the semiconductor device with a spin-on dielectric material. The spin-on dielectric material prevents conductive material from filling the crevices and causing the device to fail.

Abstract: An ultra-large scale MOS integrated circuit semiconductor device is processed after the formation of the gate oxide and polysilicon layer by forming a forming a first mask layer over the polysilicon layer followed by a second mask layer over the first mask layer. The first mask layer and the second mask layer are patterned to form first gate mask and second gate mask respectively. The polysilicon gate is then formed by anisotropically etching the polysilicon layer. The second gate mask is then removed. The polysilicon gate is then etched isotropically to reduce its width using the gate oxide layer and the patterned first gate mask as hard masks. The first gate mask is then used as a mask for dopant implantation to form source and drain extensions which are spaced away from the edges of the polysilicon gate. Thereafter, the first gate mask is removed and a spacer is formed dopant implantation to form deep source and drain junctions.

Abstract: A semiconductor wafer optical scanning system and method for determining defects on a semiconductor wafer is disclosed. The method for determining wafer defects is based on maximum allowable defects on a swath basis, rather than maximum allowable defects on a wafer basis. The method step include determining the scanned area of an individual swath that is based on a recipe set-up, consistent with the capability of the optical scanning equipment being used and the particular semiconductor wafer being tested for defects. The predetermined swath area is supplied and stored in the optical scanning system along with the maximum allowable defect density determined by the user. By using the predetermined maximum allowable defects for a swath as a limit, defect analysis may be performed on the entire wafer. The optical scanning system would stop acquiring defects for the current swath being analyzed whenever the defect limit is reached, or until the swath defect analysis has been completed.