Abstract: Methods, system and apparatus for determining shortest path bridging (SPB) of multicast frames within a communications network.

Abstract: A technique for operating a network involves controlling the black-holing of traffic by forcing customer source MAC address (CMAC)-to-backbone source MAC address (BMAC) associations at provider backbone bridge (PBB) provider edge (PE) devices to be flushed from their corresponding forwarding information bases (FIBs) in response to a service failure so that new CMAC-to-BMAC associations, which are reflective of a secondary traffic path, are learned faster than they would otherwise be learned if the network had relied on native functionality to learn new CMAC-to-BMAC associations that are reflective of the secondary traffic path.

Abstract: Providing redundancy between an active component and a standby component in a network router comprises maintaining a first route input information base associated with the active component, synchronizing with the first route information base a second route input information base associated with the standby component, generating a route output information base using the second route input information base, and comparing the generated route output information base, in the event of switchover of the standby component to an active mode, to a synchronized route output information base associated with the standby component which synchronized route output information base reflects routes known to have been shared with one or more peers by the active component prior to the switchover, and sharing and/or withdrawing routes as necessary to reflect any differences between the generated route output information base and the synchronized route output information base.

Abstract: A technique for operating a network involves controlling the black-holing of traffic by forcing customer source MAC address (CMAC)-to-backbone source MAC address (BMAC) associations at provider backbone bridge (PBB) provider edge (PE) devices to be flushed from their corresponding forwarding information bases (FIBs) in response to a service failure so that new CMAC-to-BMAC associations, which are reflective of a secondary traffic path, are learned faster than they would otherwise be learned if the network had relied on native functionality to learn new CMAC-to-BMAC associations that are reflective of the secondary traffic path.

Abstract: A technique for operating a network involves controlling the black-holing of traffic by selectively redirecting unicast traffic destined for a dual-homed customer equipment (CE) device from a first provider backbone bridge (PBB) provider edge (PE) device to a second PBB PE device in response to a service failure. Unicast traffic is selectively redirected from the first PBB PE device to the second PBB PE device for a time interval that is long enough to enable the customer source MAC address (CMAC)-to-backbone MAC address (BMAC) association of the second PBB PE device to be learned by other PBB PE devices.

Abstract: Providing redundancy between an active component and a standby component in a network router comprises maintaining a first route input information base associated with the active component, synchronizing with the first route information base a second route input information base associated with the standby component, generating a route output information base using the second route input information base, and comparing the generated route output information base, in the event of switchover of the standby component to an active mode, to a synchronized route output information base associated with the standby component which synchronized route output information base reflects routes known to have been shared with one or more peers by the active component prior to the switchover, and sharing and/or withdrawing routes as necessary to reflect any differences between the generated route output information base and the synchronized route output information base.

Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.

Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.

Abstract: A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity.

Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.

Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.

Abstract: A new method of etching metal lines with reduced microloading effect is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer and a metal layer is deposited overlying the barrier metal layer. The metal layer is covered with a photoresist mask wherein there are both wide spaces and narrow spaces between portions of the photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask wherein the barrier metal layer is reached within the wide spaces while some of the metal layer remains within the narrow spaces. The metal layer remaining within the narrow spaces is selectively etched away. Thereafter, the barrier metal layer not covered by the photoresist mask is etched away wherein the insulating layer is reached within the wide spaces while some of the barrier metal layer remains within the narrow spaces.

Abstract: A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.

Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. An integrated circuit wafer according to the present invention includes a substrate having first and second surfaces constructed from a wafer material, the first surface having a circuit layer that includes integrated circuit elements constructed thereon. A plurality of vias extend from the first surface through the circuit layer and terminate in the substrate at a first distance from the first surface. The vias include a stop layer located in the bottom of each via constructed from a stop material that is more resistant to chemical/mechanical polishing (CMP) than the wafer material. The vias may be filled with an electrically conducting material to provide vertical connections between the various circuit layers in a stacked integrated circuit.

Abstract: A new method of forming a dual damascene interconnect structure, wherein damage of interconnect and contamination of dielectrics during etching is minimized by having an embedded organic stop layer over the lower interconnect and later etching the organic stop layer with an H2 containing plasma, or hydrogen radical.

Abstract: A method is disclosed for removing metal from semiconductor substrates, optionally with or without the use of an abrasive slurry, and the attendant problems of defects caused by mechanical scratches, chemical corrosion and oxidation of components as is normally encountered with the well-known chemical-mechanical polishing (CMP) techniques. The metal removal is accomplished by placing a substrate having the metal layer in an electrolytic system in a tank, and rotating a pad against the substrate while passing current through the system including a cathode and the anodic metal layer. Preferably, the pad size is smaller than that of the substrate. The action of the pad against the metal layer moves an additive in the electrolytic solution from high regions to low regions on the metal layer, thus exposing the high regions to be polished away until all the regions are planarized to molecular height of the additive across the whole metal layer.

Abstract: A method of preventing metal penetration and diffusion from metal structures formed over a semiconductor structure, comprising the following steps. A semiconductor structure including a patterned dielectric layer is provided. The patterned dielectric layer includes an opening and an upper surface. The dielectric layer surface is then passivated to form a passivation layer. A metal plug is formed within the dielectric layer opening. The passivation layer prevents penetration and diffusion of metal out from the metal plug into the semiconductor structure and the patterned dielectric layer.