Abstract: Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be included in a computer system. A plurality of switches is coupled between the command address bus (which is coupled to the memory controller) and a respective plurality of memory modules. Each switch provides command address bus data only to its respective memory module. Preferably, only one switch does so at a time, limiting the loading seen by the memory controller.

Abstract: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.

Abstract: Embodiments herein may enable an algorithmic pattern generator (APG) to present iterative values of one or more operational parameters to a device under test (DUT). At each iteration, one or more test patterns may be presented to the DUT. The APG may capture test results from a set of iterations of the operational parameters. The APG may also write values associated with a next operational parameter to be iterated to a test parameter configuration space within the device tester.

Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.

Abstract: Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be included in a computer system. A plurality of switches is coupled between the command address bus (which is coupled to the memory controller) and a respective plurality of memory modules. Each switch provides command address bus data only to its respective memory module. Preferably, only one switch does so at a time, limiting the loading seen by the memory controller.

Abstract: A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.

Abstract: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

Abstract: Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias.

Abstract: Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.

Abstract: A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.

Abstract: Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.

Abstract: An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the relative timing between read data and data strobe signals applied to a memory device. The relative timing between the read data and data strobe signals is determined by using a delay line to delay the data strobe signal over a range of delays, and determining a final delay that causes the transitions of the delayed data strobe signal to coincide with the transitions of the read data signals. The time corresponding to the final delay is then determined by using a phase interpolator to generate a range of phase offset signals having known delay times until a phase offset signal has the same delay as the final delay.

Abstract: A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.

Abstract: A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.

Abstract: A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite surfaces being interconnected. A memory hub mounted on each module alters the configuration of address and/or command signals coupled to the memory devices depending upon whether the memory devices on the first surface of the substrate or the memory devices on the second surface of the substrate are being accessed. Alternatively, the configuration of the address and/or command signals coupled to mirrored memory devices may be altered by a register mounted on the substrate that is coupled to the memory devices or by a memory controller coupled directly to memory devices on one or more memory modules.

Abstract: A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing circuit includes a ring buffer into which the respective memory device signal is latched responsive to a first clock signal. The particular buffer into which the memory device signal is latched is determined by a write pointer, which is incremented by the first clock signal. The outputs of the buffers are applied to a multiplexer, which is controlled by a read pointer to couple a memory device signal from one of the buffers to the memory device. The read pointer is incremented by a second clock signal having a timing that is adjustable and may be different from the second clock signal used to increment the read pointer in a clock domain crossing circuit for a different memory device signal.

Abstract: A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.

Abstract: A method and apparatus for controlling the on-die termination of a memory system. The method comprises snooping a command bus in response to a first plurality of command signals clocked at 1T and enabling the on-die termination in response to a second plurality of command signals clocked at 2T and the first plurality of command signals. The apparatus may be a memory device comprising a memory array responsive to a plurality of command signals, a data bus having at least one of a data pad, a data strobe output pad, and an input data mask pad, an activation circuit responsive to certain of the plurality of command signals and operable to produce a control signal, and a termination circuit responsive to the control signal and operable to apply an effective resistance to at least one of the data pad, the data strobe output pad, and the input data mask pad.

Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.

Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.