Patents by Inventor Paul LaBerge

Paul LaBerge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory devices with buffered command address bus
    Patent number: 7149841
    Abstract: Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be included in a computer system. A plurality of switches is coupled between the command address bus (which is coupled to the memory controller) and a respective plurality of memory modules. Each switch provides command address bus data only to its respective memory module. Preferably, only one switch does so at a time, limiting the loading seen by the memory controller.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: December 12, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Paul A LaBerge
  • Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
    Patent number: 7139852
    Abstract: A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and applying a data bus inversion signal on the data masking pin, the data bus inversion signal indicating whether the data contained each read data word has been inverted. Another method and system transfer data over a data bus. The method includes generating a sequence of data words, at least one data word including data bus inversion data. The sequence of data words is applied on the data bus and is thereafter stored. The data bus inversion data is applied to invert or not invert the data contained in the stored data words.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: November 21, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. LaBerge
  • Modified persistent auto precharge command protocol system and method for memory devices
    Patent number: 7124260
    Abstract: A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the memory device, and disabling the persistent auto precharge mode of operation in response to the applied disable command. Memory devices operating according this method may be used in memory systems that infrequently experience page hits, such as server systems, while the ability to disable the persistent auto precharge mode allows such memory devices to be used in systems that frequently experience page hits, such as graphics or input/output applications.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: October 17, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. LaBerge, Jeffery W. Janzen
  • Modified persistent auto precharge command protocol system and method for memory devices
    Publication number: 20060203584
    Abstract: A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the memory device, and disabling the persistent auto precharge mode of operation in response to the applied disable command. Memory devices operating according this method may be used in memory systems that infrequently experience page hits, such as server systems, while the ability to disable the persistent auto precharge mode allows such memory devices to be used in systems that frequently experience page hits, such as graphics or input/output applications.
    Type: Application
    Filed: May 3, 2006
    Publication date: September 14, 2006
    Inventors: Paul LaBerge, Jeffery Janzen
  • System and method for read synchronization of memory modules
    Publication number: 20060206679
    Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.
    Type: Application
    Filed: May 10, 2006
    Publication date: September 14, 2006
    Inventors: Joseph Jeddeloh, Paul LaBerge
  • System and method for an asynchronous data buffer having buffer write and read pointers
    Publication number: 20060200642
    Abstract: A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.
    Type: Application
    Filed: May 4, 2006
    Publication date: September 7, 2006
    Inventor: Paul LaBerge
  • Method and apparatus for data transfer
    Patent number: 7076678
    Abstract: A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the memory. The adaptive timing system captures data in a data valid window (DVW) in a data signal. In one embodiment, the adaptive timing system comprises a delay circuit for sampling the data signal at a midpoint of the DVW. The adaptive timing system may also comprise an identifying circuit for identifying whether the midpoint of the DVW corresponds to an actual midpoint of the DVW and adjusting the delay circuit accordingly.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: July 11, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. LaBerge
  • METHOD AND APPARATUS FOR DATA TRANSFER
    Publication number: 20060129865
    Abstract: A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the memory. The adaptive timing system captures data in a data valid window (DVW) in a data signal. In one embodiment, the adaptive timing system comprises a delay circuit for sampling the data signal at a midpoint of the DVW. The adaptive timing system may also comprise an identifying circuit for identifying whether the midpoint of the DVW corresponds to an actual midpoint of the DVW and adjusting the delay circuit accordingly.
    Type: Application
    Filed: January 30, 2006
    Publication date: June 15, 2006
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Paul LaBerge
  • Latency reduction using negative clock edge and read flags
    Patent number: 7055012
    Abstract: A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because different memory devices may have different CAS latencies, a system CAS latency is selected wherein the system CAS latency is the fastest common CAS latency of each of the plurality of memory devices. After a read request is delivered to a memory device, the memory controller initiates a transmission flag to the memory device at a time equal to the system CAS latency, indicating that it is safe to transmit the requested data from the memory device to the memory controller. The transmission flags may be used in conjunction with mode registers such that one or both of the transmission flag and the data may be received by or delivered by a corresponding memory device.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 30, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. LaBerge, Jeff W. Janzen
  • Delay line synchronizer apparatus and method
    Publication number: 20060066375
    Abstract: A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.
    Type: Application
    Filed: November 14, 2005
    Publication date: March 30, 2006
    Inventor: Paul LaBerge
  • System and method for an asynchronous data buffer having buffer write and read pointers
    Publication number: 20050286506
    Abstract: A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.
    Type: Application
    Filed: June 4, 2004
    Publication date: December 29, 2005
    Inventor: Paul LaBerge
  • Delay line synchronizer apparatus and method
    Patent number: 6980042
    Abstract: A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: December 27, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. LaBerge
  • On-die termination snooping for 2T applications in a dynamic random access memory device
    Publication number: 20050268059
    Abstract: A method and apparatus for controlling the on-die termination of a memory system. The method comprises snooping a command bus in response to a first plurality of command signals clocked at 1T and enabling the on-die termination in response to a second plurality of command signals clocked at 2T and the first plurality of command signals. The apparatus may be memory device comprising a memory array responsive to a plurality of command signals, a data bus having at least one of a data pad, a data strobe output pad, and an input data mask pad, an activation circuit responsive to certain of the plurality of command signals and operable to produce a control signal, and an termination circuit responsive to the control signal and operable to apply an effective resistance to at least one of the data pad, the data strobe output pad, and the input data mask pad.
    Type: Application
    Filed: May 25, 2004
    Publication date: December 1, 2005
    Inventor: Paul LaBerge
  • DELAY LINE SYNCHRONIZER APPARATUS AND METHOD
    Publication number: 20050218956
    Abstract: A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.
    Type: Application
    Filed: April 5, 2004
    Publication date: October 6, 2005
    Inventor: Paul LaBerge
  • Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
    Publication number: 20050182894
    Abstract: A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and applying a data bus inversion signal on the data masking pin, the data bus inversion signal indicating whether the data contained each read data word has been inverted. Another method and system transfer data over a data bus. The method includes generating a sequence of data words, at least one data word including data bus inversion data. The sequence of data words is applied on the data bus and is thereafter stored. The data bus inversion data is applied to invert or not invert the data contained in the stored data words.
    Type: Application
    Filed: March 16, 2005
    Publication date: August 18, 2005
    Inventor: Paul LaBerge
  • Dynamic command and/or address mirroring system and method for memory modules
    Publication number: 20050177690
    Abstract: A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite surfaces being interconnected. A memory hub mounted on each module alters the configuration of address and/or command signals coupled to the memory devices depending upon whether the memory devices on the first surface of the substrate or the memory devices on the second surface of the substrate are being accessed. Alternatively, the configuration of the address and/or command signals coupled to mirrored memory devices may be altered by a register mounted on the substrate that is coupled to the memory devices or by a memory controller coupled directly to memory devices on one or more memory modules.
    Type: Application
    Filed: February 5, 2004
    Publication date: August 11, 2005
    Inventor: Paul LaBerge
  • System and method for read synchronization of memory modules
    Publication number: 20050149774
    Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 7, 2005
    Inventors: Joseph Jeddeloh, Paul LaBerge
  • Bus arbitration using monitored windows of time
    Patent number: 6910088
    Abstract: A method for use with a computer system includes permitting a first bus agent to access a bus during predetermined windows of time and preventing a second bus agent from accessing the bus outside of the windows. The first bus agent has a higher priority than the second bus agent. The method includes monitoring the use of the bus by the first bus agent during the window and the regulation durations of the windows are selectively regulated based on the use.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: June 21, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. LaBerge
  • Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
    Patent number: 6898648
    Abstract: A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and applying a data bus inversion signal on the data masking pin, the data bus inversion signal indicating whether the data contained each read data word has been inverted. Another method and system transfer data over a data bus. The method includes generating a sequence of data words, at least one data word including data bus inversion data. The sequence of data words is applied on the data bus and is thereafter stored. The data bus inversion data is applied to invert or not invert the data contained in the stored data words.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: May 24, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. LaBerge
  • System and method for multiplexing data and data masking information on a data bus of a memory device
    Patent number: 6888760
    Abstract: A method and system masking data being written to a memory device having a data bus. One method includes applying masking data on the data bus, storing the masking data in the memory device, applying write data on the data bus, storing the write data in the memory device, and applying the stored masking data to mask the stored write data.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: May 3, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. LaBerge