Patents by Inventor Paul Langner

Paul Langner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11119967
    Abstract: A system including an Ethernet transceiver PHY and a network device is disclosed. The Ethernet transceiver PHY includes register circuitry to store information associated with operating characteristics of the PHY. The network device couples to the Ethernet transceiver PHY in a closed system architecture and includes a system processor and an MDIO interface. The MDIO interface interacts with the PHY register circuitry during a normal operating mode. The system includes system interface circuitry to receive requests for accessing the register circuitry in a debug operating mode. The requests are generated external to the closed system architecture.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: September 14, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Paul Langner
  • Patent number: 11055244
    Abstract: An input/output (I/O) interface system for computing devices is disclosed. The I/O interface system includes an externally-engageable USB-C interface connector. A first I/O protocol controller circuit couples to the USB-C interface connector via multiple bidirectional serial lanes. Each of the bidirectional serial lanes transfers a single serial stream of data in a simultaneously bidirectional manner. A second I/O protocol controller circuit couples to the USB-C interface connector via multiple unidirectional serial lanes. Each of the unidirectional serial lanes transfers a single serial stream of data in a unidirectional manner. Mode control circuitry selects between the first I/O protocol controller circuit and the second I/O protocol controller circuit for data transfers with the USB-C interface connector based on a detected signaling media externally connected to the USB-C interface connector.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: July 6, 2021
    Assignee: Marvell Asia Pte, LTD.
    Inventors: Paul Langner, Simon Edelhaus
  • Publication number: 20210111932
    Abstract: A multi-chip module (MCM) includes a first integrated circuit (IC) chip to receive first data. The first IC chip includes a first transfer interface to transmit the first data off the first IC chip. A second IC chip includes an input interface to receive the first data from the first IC chip. The second IC chip includes switching circuitry to selectively forward the first data to one of a first output interface or a second output interface. The first output interface is communicatively coupled to a third IC chip, while the second output interface is configured to output the first data from the MCM.
    Type: Application
    Filed: December 1, 2020
    Publication date: April 15, 2021
    Inventors: Ramin Farjadrad, Paul Langner
  • Publication number: 20210044460
    Abstract: An Ethernet link is disclosed. The link includes a first Ethernet transceiver and a second Ethernet transceiver configured as a link partner to the first Ethernet transceiver. A shielded twisted quad (STQ) cable is interposed between the first Ethernet transceiver and the second Ethernet transceiver. The STQ cable includes four conductors, each conductor having a first end interfaced with a corresponding input/output (I/O) circuit of the first Ethernet transceiver in a single-ended configuration, and a second end interfaced with a corresponding input/output (I/O) circuit of the second Ethernet transceiver in a single-ended configuration.
    Type: Application
    Filed: July 21, 2020
    Publication date: February 11, 2021
    Inventor: Paul Langner
  • Publication number: 20200403726
    Abstract: A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and, forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits. A symbol mapper modulates the Ethernet block data bits in accordance with an SQ64 constellation comprising back-to-back PAM8 symbols.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 24, 2020
    Inventors: Ramin FARJADRAD, Paul LANGNER
  • Patent number: 10855395
    Abstract: Methods and apparatus for transmitting Ethernet data along an Ethernet link with a BASE-T transceiver are disclosed. One exemplary BASE-T Ethernet transceiver includes an Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate. Logic associates the Ethernet block data bits with an auxiliary bit and a number of zero bits. An error encoder is coupled to the logic to encode all of the data bits, auxiliary bit and zero bits into an error encoded transport frame having plural error check bits. A symbol mapper receives the error encoded transport frame and transforms the error encoded transport frame into multiple symbols. A transmitter coupled to the symbol mapper transmits the multiple symbols over an Ethernet link at one of a selection of symbol rates. The data rate of data transmitted over the Ethernet link is based on the number of zero bits.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: December 1, 2020
    Assignee: Marvell Asia Pte, LTD.
    Inventors: Ramin Farjadrad, Paul Langner, Hossein Sedarat, Ramin Shirani, Kamal Dalmia
  • Patent number: 10855498
    Abstract: A packaged semiconductor device includes a substrate and first, second, and third integrated circuit (IC) chips. The first integrated circuit (IC) chip is mounted on the substrate to receive first data and includes a first transfer interface to transmit the first data via first conductors formed in the substrate. The second IC chip mounts on the substrate and has a second transfer interface to receive the first data. The second IC includes on-chip conductors to route the first data on-chip to an output interface. The output interface transmits the first data via second conductors formed on the substrate. A third IC chip mounts on the substrate and has a third transfer interface to receive the first data via the second conductors.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: December 1, 2020
    Assignee: Marvell Asia Pte, LTD
    Inventors: Ramin Farjadrad, Paul Langner
  • Patent number: 10754409
    Abstract: An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry including transmit circuitry, receive circuitry, and adaptive filters. The transceiver circuitry is configurable to operate in one of two low-power modes. A first low-power mode includes update operations for the adaptive filters. A second low-power mode includes turning off at least one of the transmit circuitry and the receive circuitry, and omitting update operations for the adaptive filters.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 25, 2020
    Assignee: Marvell Asia Pte., LTD.
    Inventors: Saied Benyamin, Paul Langner, George Zimmerman
  • Patent number: 10721101
    Abstract: An Ethernet link is disclosed. The link includes a first Ethernet transceiver and a second Ethernet transceiver configured as a link partner to the first Ethernet transceiver. A shielded twisted quad (STQ) cable is interposed between the first Ethernet transceiver and the second Ethernet transceiver. The STQ cable includes four conductors, each conductor having a first end interfaced with a corresponding input/output (I/O) circuit of the first Ethernet transceiver in a single-ended configuration, and a second end interfaced with a corresponding input/output (I/O) circuit of the second Ethernet transceiver in a single-ended configuration.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: July 21, 2020
    Assignee: Marvell Asia Pte, LTD
    Inventor: Paul Langner
  • Publication number: 20200228229
    Abstract: Methods and apparatus for transmitting Ethernet data along an Ethernet link with a BASE-T transceiver are disclosed. One exemplary BASE-T Ethernet transceiver includes an Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate. Logic associates the Ethernet block data bits with an auxiliary bit and a number of zero bits. An error encoder is coupled to the logic to encode all of the data bits, auxiliary bit and zero bits into an error encoded transport frame having plural error check bits. A symbol mapper receives the error encoded transport frame and transforms the error encoded transport frame into multiple symbols. A transmitter coupled to the symbol mapper transmits the multiple symbols over an Ethernet link at one of a selection of symbol rates. The data rate of data transmitted over the Ethernet link is based on the number of zero bits.
    Type: Application
    Filed: March 23, 2020
    Publication date: July 16, 2020
    Inventors: Ramin FARJADRAD, Paul LANGNER, Hossein SEDARAT, Ramin SHIRANI, Kamal Dalmia
  • Patent number: 10673561
    Abstract: A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and, forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits. A symbol mapper modulates the Ethernet block data bits in accordance with an SQ64 constellation comprising back-to-back PAM8 symbols.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 2, 2020
    Assignee: Marvell Asia Pte, LTD
    Inventors: Ramin Farjad, Paul Langner
  • Patent number: 10601542
    Abstract: Methods and apparatus for transmitting Ethernet data along an Ethernet link with a BASE-T transceiver are disclosed. One exemplary BASE-T Ethernet transceiver includes an Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate. Logic associates the Ethernet block data bits with an auxiliary bit and a number of zero bits. An error encoder is coupled to the logic to encode all of the data bits, auxiliary bit and zero bits into an error encoded transport frame having plural error check bits. A symbol mapper receives the error encoded transport frame and transforms the error encoded transport frame into multiple symbols. A transmitter coupled to the symbol mapper transmits the multiple symbols over an Ethernet link at one of a selection of symbol rates. The data rate of data transmitted over the Ethernet link is based on the number of zero bits.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: March 24, 2020
    Assignee: Marvell Asia Pte, LTD.
    Inventors: Ramin Farjadrad, Paul Langner, Hossein Sedarat, Ramin Shirani, Kamal Dalmia
  • Patent number: 10148508
    Abstract: A method of signaling between Ethernet transceivers along a link is disclosed. The method includes advertising first and second supported data rates between the transceivers during an autonegotiation sequence. The link is then trained to train transceiver operating parameters with a training sequence of symbols. The training includes initiating the training sequence to support the first data rate, determining whether the link can operate at the first data rate, and transferring control information requesting a retrain at a second data rate different than the first data rate if the link cannot support the first data rate. The link is retrained, in response to the control information, to train the parameters for operation at the second data rate. The retraining is carried out without repeating the autonegotiation sequence. The link is then operated in a data transfer mode at the second data rate.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: December 4, 2018
    Assignee: Aquantia Corp.
    Inventors: Hossein Sedarat, Paul Langner, Ramin Farjadrad, Kamal Dalmia
  • Patent number: 10063341
    Abstract: Methods and apparatus for transmitting Ethernet data along an Ethernet link with a BASE-T transceiver are disclosed. One exemplary BASE-T Ethernet transceiver includes an Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate. Logic associates the Ethernet block data bits with an auxiliary bit and a number of zero bits. An error encoder is coupled to the logic to encode all of the data bits, auxiliary bit and zero bits into an error encoded transport frame having plural error check bits. A symbol mapper receives the error encoded transport frame and transforms the error encoded transport frame into multiple symbols. A transmitter coupled to the symbol mapper transmits the multiple symbols over an Ethernet link at one of a selection of symbol rates. The data rate of data transmitted over the Ethernet link is based on the number of zero bits.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 28, 2018
    Assignee: Aquantia Corp.
    Inventors: Ramin Farjadrad, Paul Langner, Hossein Sedarat, Ramin Shirani, Kamal Dalmia
  • Patent number: 9853769
    Abstract: A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and, forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits. A symbol mapper modulates the Ethernet block data bits in accordance with an SQ64 constellation comprising back-to-back PAM8 symbols.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: December 26, 2017
    Inventors: Ramin Farjad, Paul Langner
  • Patent number: 9774420
    Abstract: A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and logic to aggregate the Ethernet block data bits in accordance with a 512/513B code. A forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: September 26, 2017
    Assignee: Aquantia Corp.
    Inventor: Paul Langner
  • Patent number: 9634800
    Abstract: A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate, logic to associate the Ethernet block data bits with an auxiliary bit and a number of Reed-Solomon check bytes, and a forward error correction encoder. The encoder is coupled to the logic to encode all of the data bits, auxiliary bit and the Reed-Solomon check bytes into a first error encoded transport frame having plural error check bits. A symbol mapper receives the first error encoded transport frame and modulates the first error encoded transport frame into symbols, each of the symbols having uncoded bits. A BASE-T transmitter is coupled to the symbol mapper to transmit the first group of symbols over an Ethernet link at one of a selection of symbol rates. Errors in the uncoded bits are correctable via the Reed-Solomon check bytes.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: April 25, 2017
    Assignee: Aquantia Corp.
    Inventors: Paul Langner, Hossein Sedarat
  • Patent number: 9485335
    Abstract: A method of operation in a high-speed Ethernet transceiver is disclosed. The method includes engaging in an autonegotiation process with a link partner transceiver to indicate whether one or more sub-rate modes of operation are supported. Each sub-rate mode of operation corresponds to a sub-data rate that is less than a maximum data rate. The autonegotiation process is terminated. The transceiver then participates in a training process. The training process includes receiving a first training sequence corresponding to a first sub-data rate that is less than the maximum data rate. A signal quality parameter for the received first training sequence is measured. The training sequence is terminated based on the measured signal quality parameter failing a predetermined criteria. A second training sequence is then initiated that corresponds to a second sub-data rate that is less than the first sub-data rate without starting a second autonegotiation process.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: November 1, 2016
    Assignee: Aquantia Corp.
    Inventors: Paul Langner, Hossein Sedarat
  • Patent number: 9363039
    Abstract: Methods and apparatus for transmitting Ethernet data along an Ethernet link with a BASE-T transceiver are disclosed. One exemplary BASE-T Ethernet transceiver includes an Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate. Logic associates the Ethernet block data bits with an auxiliary bit and a number of zero bits. An error encoder is coupled to the logic to encode all of the data bits, auxiliary bit and zero bits into an error encoded transport frame having plural error check bits. A symbol mapper receives the error encoded transport frame and transforms the error encoded transport frame into multiple symbols. A transmitter coupled to the symbol mapper transmits the multiple symbols over an Ethernet link at one of a selection of symbol rates. The data rate of data transmitted over the Ethernet link is based on the number of zero bits.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: June 7, 2016
    Assignee: Aquantia Corp.
    Inventors: Ramin Farjadrad, Paul Langner, Hossein Sedarat, Ramin Shirani, Kamal Dalmia
  • Patent number: 9281916
    Abstract: Methods and apparatus for transferring data along a link with a 10GBASE-T transceiver at a variable data rate are disclosed. One exemplary method includes detecting a link quality metric; and selecting a symbol transmission rate and a data modulation scheme based on the detected link quality metric. In many implementations, for a selected symbol transmission rate, if the detected link quality metric is less than a link quality threshold, then the selecting of the data modulation scheme is performed such that a data bit per symbol value represented by the selected data modulation scheme is decreased by at least ½ data bit per symbol. The selected symbol transmission rate and the selected modulation together represent a selectable data rate from a selection of data rates.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 8, 2016
    Assignee: Aquantia Corp.
    Inventors: Ramin Farjadrad, Paul Langner, Hossein Sedarat, Ramin Shirani, Kamal Dalmia