Patents by Inventor Paul M. Enquist
Paul M. Enquist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10748824Abstract: Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.Type: GrantFiled: December 3, 2019Date of Patent: August 18, 2020Assignee: Invensas Bonding Technologies, Inc.Inventors: Javier A. Delacruz, Paul M. Enquist, Gaius Gillman Fountain, Jr., Ilyas Mohammed
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Publication number: 20200144217Abstract: A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element.Type: ApplicationFiled: December 20, 2019Publication date: May 7, 2020Inventors: Paul M. Enquist, Liang Wang, Rajesh Katkar, Javier A. DeLaCruz, Arkalgud R. Sitaram
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Publication number: 20200105630Abstract: Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.Type: ApplicationFiled: December 3, 2019Publication date: April 2, 2020Inventors: Javier A. DELACRUZ, Paul M. ENQUIST, Gaius Gillman FOUNTAIN, JR., Ilyas MOHAMMED
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Patent number: 10607937Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.Type: GrantFiled: April 18, 2019Date of Patent: March 31, 2020Assignee: Invensas Bonding Technologies, Inc.Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Javier A. DeLaCruz
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Publication number: 20200043910Abstract: Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.Type: ApplicationFiled: October 11, 2019Publication date: February 6, 2020Inventors: Cyprian Emeka Uzoh, Paul M. Enquist, Gaius Gillman Fountain, JR.
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Patent number: 10529634Abstract: Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.Type: GrantFiled: December 11, 2017Date of Patent: January 7, 2020Assignee: Invensas Bonding Technologies, Inc.Inventors: Javier A. Delacruz, Paul M. Enquist, Gaius Gillman Fountain, Jr., Ilyas Mohammed
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Patent number: 10522499Abstract: A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element.Type: GrantFiled: December 20, 2017Date of Patent: December 31, 2019Assignee: Invensas Bonding Technologies, Inc.Inventors: Paul M. Enquist, Liang Wang, Rajesh Katkar, Javier A. DeLaCruz, Arkalgud R. Sitaram
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Publication number: 20190355706Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.Type: ApplicationFiled: May 15, 2019Publication date: November 21, 2019Inventors: Paul M. Enquist, Belgacem HABA
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Patent number: 10446532Abstract: Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.Type: GrantFiled: December 22, 2016Date of Patent: October 15, 2019Assignee: Invensas Bonding Technologies, Inc.Inventors: Cyprian Emeka Uzoh, Paul M. Enquist, Gaius Gillman Fountain, Jr.
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Publication number: 20190244899Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.Type: ApplicationFiled: April 18, 2019Publication date: August 8, 2019Inventors: Paul M. Enquist, Gaius Gillman Fountain, JR., Javier A. DeLaCruz
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Publication number: 20190237419Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.Type: ApplicationFiled: April 12, 2019Publication date: August 1, 2019Inventor: Paul M. ENQUIST
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Patent number: 10366962Abstract: A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.Type: GrantFiled: December 20, 2016Date of Patent: July 30, 2019Assignee: Invensas Bonding Technologies, Inc.Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr.
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Patent number: 10312217Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.Type: GrantFiled: July 8, 2016Date of Patent: June 4, 2019Assignee: Invensas Bonding Technologies, Inc.Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
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Publication number: 20190148222Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.Type: ApplicationFiled: November 30, 2018Publication date: May 16, 2019Inventors: Paul M. Enquist, Gaius Gillman Fountain, JR., Qin-Yi Tong
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Patent number: 10269708Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.Type: GrantFiled: December 22, 2017Date of Patent: April 23, 2019Assignee: Invensas Bonding Technologies, Inc.Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Javier A. DeLaCruz
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Publication number: 20190115247Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.Type: ApplicationFiled: November 21, 2018Publication date: April 18, 2019Inventors: Qin-Yi Tong, Paul M. Enquist, Anthony Scot Rose
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Patent number: 10262963Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.Type: GrantFiled: April 6, 2018Date of Patent: April 16, 2019Assignee: Invensas Bonding Technologies, Inc.Inventor: Paul M. Enquist
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Patent number: 10147641Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.Type: GrantFiled: July 18, 2017Date of Patent: December 4, 2018Assignee: INVENSAS BONDING TECHNOLOGIES, INC.Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Qin-Yi Tong
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Patent number: 10141218Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.Type: GrantFiled: December 4, 2015Date of Patent: November 27, 2018Assignee: INVENSAS BONDING TECHNOLOGIES, INC.Inventors: Qin-Yi Tong, Paul M. Enquist, Anthony Scot Rose
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Publication number: 20180331000Abstract: Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.Type: ApplicationFiled: December 11, 2017Publication date: November 15, 2018Inventors: Javier A. DELACRUZ, Paul M. ENQUIST, Gaius Gillman FOUNTAIN, JR., Ilyas MOHAMMED