Patents by Inventor Paul M. Solomon

Paul M. Solomon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804261
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jin-Ping Han, Yulong Li, Dennis M. Newns, Paul M. Solomon, Xiao Sun
  • Patent number: 10777645
    Abstract: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy M. Cohen, Paul M. Solomon, Christian Lavoie
  • Patent number: 10755759
    Abstract: A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin M. Frank, Jin-Ping Han, Dennis M. Newns, Paul M. Solomon, Xiao Sun
  • Publication number: 20200243688
    Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Jin-Ping Han, Ramachandran Muralidhar, Dennis M. Newns, Paul M. Solomon
  • Publication number: 20200227274
    Abstract: A subtractive forming method that includes providing a material stack including a samarium and selenium containing layer and an aluminum containing layer in direct contact with the samarium and selenium containing layer. The samarium component of the samarium and selenium containing layer of the exposed portion of the material stack is etched with an etch chemistry comprising citric acid and hydrogen peroxide that is selective to the aluminum containing layer. The hydrogen peroxide reacts with the aluminum containing layer to provide an oxide etch protectant surface on the aluminum containing layer, and the citric acid etches samarium selectively to the oxide etch protectant surface. Thereafter, a remaining selenium component of is removed by elevating a temperature of the selenium component.
    Type: Application
    Filed: March 27, 2019
    Publication date: July 16, 2020
    Inventors: Christine Armstrong, Matthew W. Copel, Yu Luo, Paul M. Solomon
  • Patent number: 10680105
    Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin-Ping Han, Ramachandran Muralidhar, Dennis M. Newns, Paul M. Solomon
  • Publication number: 20200173847
    Abstract: A self-clocked photoreceiver device and a method of operating. The self-clocked photoreceiver device includes a light detector connected between a power supply node and a first node, and first to third switching elements. The light detector is configured to detect an incident optical data signal, and to output photocurrent corresponding to a magnitude of the optical data signal through the first node. The first switching element is connected between the first node and a ground node. The second switching element is connected between the power supply node and a second node. The third switching element is connected between the second node and the ground node. The third switching element has a control node connected to the first node.
    Type: Application
    Filed: February 7, 2020
    Publication date: June 4, 2020
    Inventors: Jason S. Orcutt, Paul M. Solomon
  • Publication number: 20200161545
    Abstract: A method of tuning a PCM device is disclosed. The method includes receiving a command and determining if the command is a SET command or a RESET command. When the command is a RESET command, the method provides a short pulse across a resistive electrode and a top electrode through a phase change material generating amorphous PCM at the point of highest voltage across the PCM region.
    Type: Application
    Filed: January 22, 2020
    Publication date: May 21, 2020
    Inventors: Guy M. Cohen, Paul M. Solomon
  • Publication number: 20200161436
    Abstract: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Guy M. Cohen, Paul M. Solomon, Christian Lavoie
  • Patent number: 10658384
    Abstract: A field-effect transistor includes a semiconductor substrate having first, second, third, and fourth sides, and a ferroelectric gate stack on an upper surface of the substrate. The ferroelectric gate stack includes a gate insulating layer; and a ferroelectric material layer on the gate insulating layer. Portions of the upper surface of the substrate between the first side and the ferroelectric gate stack and between the second side and the ferroelectric gate stack are doped with n-type impurities, and portions of the upper surface of the substrate between the third side and the ferroelectric gate stack and between the fourth side and the ferroelectric gate stack are doped with p-type impurities. A presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David J. Frank, Paul M. Solomon, Xiao Sun
  • Publication number: 20200152741
    Abstract: A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
    Type: Application
    Filed: January 20, 2020
    Publication date: May 14, 2020
    Inventors: Yulong Li, Paul M. Solomon, Siyuranga Koswatta
  • Publication number: 20200117984
    Abstract: Systems and methods for a capacitor based resistive processing unit with symmetrical weight updating include a first capacitor that stores a charge corresponding to a weight value. A readout circuit reads the charge stored in the first capacitor to apply a weight to an input value corresponding to an input signal using the weight value to produce an output. An update circuit updates the weight value stored in the first capacitor, including a second capacitor in communication with the first capacitor to transfer an amount of charge to the first capacitor according to an error of the output by changing a voltage difference across the first capacitor by a voltage change corresponding to the amount of charge, the voltage difference corresponding to the charge stored in the first capacitor.
    Type: Application
    Filed: October 12, 2018
    Publication date: April 16, 2020
    Inventors: Yulong Li, Paul M. Solomon, Effendi Leobandung
  • Patent number: 10615176
    Abstract: A field-effect transistor includes a semiconductor substrate having first, second, third, and fourth sides, and a ferroelectric gate stack on an upper surface of the substrate. The ferroelectric gate stack includes a gate insulating layer; and a ferroelectric material layer on the gate insulating layer. Portions of the upper surface of the substrate between the first side and the ferroelectric gate stack and between the second side and the ferroelectric gate stack are doped with n-type impurities, and portions of the upper surface of the substrate between the third side and the ferroelectric gate stack and between the fourth side and the ferroelectric gate stack are doped with p-type impurities. A presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINE CORPORATION
    Inventors: David J. Frank, Paul M. Solomon, Xiao Sun
  • Patent number: 10615261
    Abstract: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy M. Cohen, Paul M. Solomon, Christian Lavoie
  • Patent number: 10586849
    Abstract: A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yulong Li, Paul M. Solomon, Siyuranga Koswatta
  • Patent number: 10586922
    Abstract: A phase change material (PCM) device is disclosed. The PCM device includes a bottom electrode and an insulator layer over the bottom electrode. The PCM device further includes a resistive electrode over the insulator layer with a via in the insulator layer between one end of the resistive electrode and the bottom electrode. The PCM device further includes a PCM region over the resistive electrode and a top electrode over the PCM region.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy M. Cohen, Paul M. Solomon
  • Publication number: 20200066755
    Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Jin Ping Han, Ramachandran Muralidhar, Paul M. Solomon, Dennis M. Newns, Martin M. Frank
  • Publication number: 20200066980
    Abstract: A phase change material (PCM) device is disclosed. The PCM device includes a bottom electrode and an insulator layer over the bottom electrode. The PCM device further includes a resistive electrode over the insulator layer with a via in the insulator layer between one end of the resistive electrode and the bottom electrode. The PCM device further includes a PCM region over the resistive electrode and a top electrode over the PCM region.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: Guy M. Cohen, Paul M. Solomon
  • Patent number: 10571331
    Abstract: A photoreceiver device includes a light detector connected between a power supply node and a first node, and first to third switching elements. The light detector is configured to detect an incident optical data signal, and to output photocurrent corresponding to a magnitude of the optical data signal through the first node. The first switching element is connected between the first node and a ground node. The second switching element is connected between the power supply node and a second node. The third switching element is connected between the second node and the ground node. The third switching element has a control node connected to the first node.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jason S. Orcutt, Paul M. Solomon
  • Publication number: 20200058641
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Jin-Ping Han, Yulong Li, Dennis M. Newns, Paul M. Solomon, Xiao Sun