Abstract: A clip assembly (42) for securing a tubular member (5) to an endoscope (3) comprises a plurality of clips (40) tethered together by a looped tether (41). Each clip (40) comprises a first channel (48) for engaging the endoscope (3) and a second channel (50) for engaging the tubular member (5). Each clip comprises a carrier element (45) and an adapter element (47) secured to the carrier element (45). The carrier element (45) comprises a body member (52) having a pair of first side members (54) extending therefrom defining the first channel (48), and a pair of engagement side members (67) defining an engagement channel (69). The adapter element comprises an arcuate element (80) engaged in the engagement channel (69) for defining the second channel (50). A covering element (95) comprising a pair of end panels (91) extending from the arcuate element (80) cover ends (61) of the carrier element (45).

Abstract: A suturing device (1) for suturing parts (5,6) together of a lumen (8) with one or more sutures (3) comprises an actuator (34) having a handle (33) and first and second operating elements (60,68) slideable longitudinally on the handle (33). A tubular shield (35) extends from the handle (33), and a cannula (40) slideable in the tubular shield (35) is connected to the first operating element (60) for urging the cannula (40) between a withdrawn state within the tubular shield (35) to an extended state extending from the tubular shield (35). An elongated push rod (52) slideable in the cannula (40) terminating in a distal hook (55) is coupled to and operated by the second operating element (68). Anchor elements (22) of the suture (3) are located in the cannula (40), and are sequentially urged therefrom by the push rod (52), as the cannula (40) sequentially pierces through the parts (5,6).

Abstract: A computer processor is provided that employs a plurality of operand storage elements that store operand data values and associated meta-data as unitary operand data elements as well as at least one functional unit that performs operations that produce and access the unitary operand data elements stored in the plurality of operand storage elements. The meta-data associated with a given operand data value as part of a unitary operand data element can specify type of the unitary operand data element (e.g., vector or scalar), elemental width and floating-point error flags. The meta-data can also be used to define special operand data values (e.g., Not-a-Result and None). The meta-data is useful in optimizing execution, such as in speculation and vectorized SIMD operations. The computer processor can also support a number of particular vector operations that are useful in optimizing execution of vectorized SIMD operations.

Abstract: Disclosed is a method for assistance with the establishment of a diagnosis of a patient, starting from at least one identified sign, and based on a computerized knowledge database including a medical ontology. The medical ontology includes: a list of signs forming a “sign” class; a list of pathological states forming a “pathological state” class; and a first set of logical relationships between the signs and the pathological states, each logical relationship establishing a correlative link between a sign and a pathological state. The method includes: a step of searching for potential pathological states, linked to at least one of the identified signs by the first set of logical relationships; and a step of identifying potential signs in which, for each potential pathological state, all of the signs linked by a correlative link to the potential pathological state are identified by the first set of logical relationships.

Abstract: A computer processor is provided that employs a plurality of operand storage elements that store operand data values and associated meta-data as unitary operand data elements as well as at least one functional unit that performs operations that produce and access the unitary operand data elements stored in the plurality of operand storage elements. The meta-data associated with a given operand data value as part of a unitary operand data element can specify type of the unitary operand data element (e.g., vector or scalar), elemental width and floating-point error flags. The meta-data can also be used to define special operand data values (e.g., Not-a-Result and None). The meta-data is useful in optimizing execution, such as in speculation and vectorized SIMD operations. The computer processor can also support a number of particular vector operations that are useful in optimizing execution of vectorized SIMD operations.

Abstract: A computer processor employs an instruction processing pipeline that processes a sequence of wide instructions each including a plurality of encoding slots that contain a plurality of different operations. The plurality of encoding slots and the operations contained therein for each wide instruction are statically assigned to different phases of execution belonging to an ordered set of phases of execution. The ordered set of phases of execution can have a predefined order that allows data produced by execution of an operation in an earlier phase of execution to be consumed by execution of at least one other operation in a later phase of execution.

Abstract: Disclosed is a method for assistance with the establishment of a diagnosis of a patient, starting from at least one identified sign, and based on a computerized knowledge database including a medical ontology. The medical ontology includes: a list of signs forming a “sign” class; a list of pathological states forming a “pathological state” class; and a first set of logical relationships between the signs and the pathological states, each logical relationship establishing a correlative link between a sign and a pathological state. The method includes: a step of searching for potential pathological states, linked to at least one of the identified signs by the first set of logical relationships; and a step of identifying potential signs in which, for each potential pathological state, all of the signs linked by a correlative link to the potential pathological state are identified by the first set of logical relationships.

Abstract: A computer processor including a first memory structure that operates over multiple cycles to temporarily store operands referenced by at least one instruction. A plurality of functional units performs operations that produce and access operands stored in the first memory structure. A second memory structure is provided, separate from the first memory structure. The second memory structure is configured as a dedicated memory for storage of operands copied from the first memory structure. The second memory structure is organized with a byte-addressable memory space and each operand stored in the second memory structure is accessed by a given byte address into the byte-addressable memory space.

Abstract: A computer processor including a plurality of functional units that performs operations that produce result operands at different characteristic latencies over multiple cycles. An interconnect network provides data paths for transfer of operand data between functional units. The interconnect network includes first and second crossbar parts. The first crossbar part is configured to route result operands produced with the lowest characteristic latency to any other functional unit. The second crossbar part is configured to route result operands with higher characteristic latency relative to the lowest characteristic latency to the first crossbar part where such result operands are in turn routed to any functional unit. In another aspect, the functional units can be organized as multiple slots where each slot can produce multiple result operands of different characteristic latencies in the same cycle, and wherein each slot employs separate result registers for each characteristic latency present on the slot.

Abstract: A computer processor and corresponding method of operation employs execution logic that includes at least one functional unit and operand storage that stores data that is produced and consumed by the at least one functional unit. The at least one functional unit is configured to execute a deferred operation whose execution produces result data. The execution logic further includes a retire station that is configured to store and retire the result data of the deferred operation in order to store such result data in the operand storage, wherein the retire of such result data occurs at a machine cycle following issue of the deferred operation as controlled by statically-assigned parameter data included in the encoding of the deferred operation.

Abstract: A computer processor including a plurality of storage elements logically organized as a fixed length queue referenced by logical temporal addresses. The fixed length queue operates over multiple cycles to temporarily store operands referenced by at least one instruction utilizing the logical temporal addresses. A plurality of functional units performs operations over the multiple cycles, wherein the operations produce and access operands stored in the logical fixed length queue. Operands can be added to the front of the logical fixed length queue according to the temporal order that operands are produced by the functional units, and operands can drop from the end of the logical fixed length queue as operands are added to the front of the fixed length queue. A plurality of operands produced by the plurality of functional units (possibly with different latencies in producing such operands) can be added to the logical fixed length queue in a single cycle.

Abstract: A computer processor employs an instruction processing pipeline that processes a sequence of wide instructions each having an encoding that represents a plurality of different operations. The plurality of different operations of the given wide instruction are logically organized into a number of phases having a predefined ordering such that some or all of the plurality of different operations of the given wide instruction are executed as at least one dataflow. In certain circumstances where stalling is absent, the plurality of different operations of the phases of the given wide instruction can be issued for execution by the instruction processing pipeline over a plurality of consecutive machine cycles.

Abstract: A computer processor including a plurality of functional units that performs operations that produce result operands at different characteristic latencies over multiple cycles. An interconnect network provides data paths for transfer of operand data between functional units. The interconnect network includes first and second crossbar parts. The first crossbar part is configured to route result operands produced with the lowest characteristic latency to any other functional unit. The second crossbar part is configured to route result operands with higher characteristic latency relative to the lowest characteristic latency to the first crossbar part where such result operands are in turn routed to any functional unit. In another aspect, the functional units can be organized as multiple slots where each slot can produce multiple result operands of different characteristic latencies in the same cycle, and wherein each slot employs separate result registers for each characteristic latency present on the slot.

Abstract: A computer processor including a plurality of storage elements logically organized as a fixed length queue referenced by logical temporal addresses. The fixed length queue operates over multiple cycles to temporarily store operands referenced by at least one instruction utilizing the logical temporal addresses. A plurality of functional units performs operations over the multiple cycles, wherein the operations produce and access operands stored in the logical fixed length queue. Operands can be added to the front of the logical fixed length queue according to the temporal order that operands are produced by the functional units, and operands can drop from the end of the logical fixed length queue as operands are added to the front of the fixed length queue. A plurality of operands produced by the plurality of functional units (possibly with different latencies in producing such operands) can be added to the logical fixed length queue in a single cycle.

Abstract: A computer processor including a first memory structure that operates over multiple cycles to temporarily store operands referenced by at least one instruction. A plurality of functional units performs operations that produce and access operands stored in the first memory structure. A second memory structure is provided, separate from the first memory structure. The second memory structure is configured as a dedicated memory for storage of operands copied from the first memory structure. The second memory structure is organized with a byte-addressable memory space and each operand stored in the second memory structure is accessed by a given byte address into the byte-addressable memory space.

Abstract: A computer processor employs an instruction processing pipeline that processes a sequence of wide instructions each having an encoding that represents a plurality of different operations. The plurality of different operations of the given wide instruction are logically organized into a number of phases having a predefined ordering such that at least one operation of the given wide instruction produces data that is consumed by at least one other operation of the given wide instruction. In certain circumstances where stalling is absent, the plurality of different operations of the phases of the given wide instruction can be issued for execution by the instruction processing pipeline over a plurality of consecutive machine cycles.

Abstract: A computer processor is provided that employs a plurality of operand storage elements that store operand data values and associated meta-data as unitary operand data elements as well as at least one functional unit that performs operations that produce and access the unitary operand data elements stored in the plurality of operand storage elements. The meta-data associated with a given operand data value as part of a unitary operand data element can specify type of the unitary operand data element (e.g., vector or scalar), elemental width and floating-point error flags. The meta-data can also be used to define special operand data values (e.g., Not-a-Result and None). The meta-data is useful in optimizing execution, such as in speculation and vectorized SIMD operations. The computer processor can also support a number of particular vector operations that are useful in optimizing execution of vectorized SIMD operations.

Abstract: A material dispenser includes a base, a platen, a spring, a casing, a material pick-up mechanism, and a cap. The spring is connected in between the platen and the base, and the casing encloses the spring and the platen and removably attaches with the base. The material pick-up mechanism is rotatably connected with the casing opposite from the base. The cap attaches with the casing opposite from the base and positions adjacent with the material pick-up mechanism. The material dispenser includes stored materials in between the platen and the material pick-up mechanism. The casing provides a parameter wall for the stored materials. The users of the material dispenser can dispense an exact amount of the stored materials through a top opening of the casing by rotating the material pick-up mechanism.