Patents by Inventor Paul Metzgen
Paul Metzgen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200026685Abstract: A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline seType: ApplicationFiled: March 26, 2019Publication date: January 23, 2020Inventor: Paul Metzgen
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Patent number: 10275390Abstract: A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline seType: GrantFiled: May 19, 2017Date of Patent: April 30, 2019Assignee: Silicon Tailor LimitedInventor: Paul Metzgen
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Publication number: 20180089140Abstract: A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline seType: ApplicationFiled: May 19, 2017Publication date: March 29, 2018Inventor: Paul Metzgen
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Patent number: 9658985Abstract: A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline seType: GrantFiled: October 28, 2014Date of Patent: May 23, 2017Assignee: Silicon Tailor LimitedInventor: Paul Metzgen
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Publication number: 20160259757Abstract: A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline seType: ApplicationFiled: October 28, 2014Publication date: September 8, 2016Inventor: Paul Metzgen
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Patent number: 8930922Abstract: A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g., RAM). This facilitates multiple reads during a single clock cycle. Symbol set analysis is used to minimize the size of regions to allow for more efficient use of hardware resources.Type: GrantFiled: September 13, 2012Date of Patent: January 6, 2015Assignee: Altera CorporationInventor: Paul Metzgen
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Patent number: 8615543Abstract: Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.Type: GrantFiled: June 22, 2011Date of Patent: December 24, 2013Assignee: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Steven Perry, Paul Metzgen, Nitin Prasad, William Hwang
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Patent number: 8473926Abstract: A software-to-hardware compiler is provided that generates hardware constructs in programmable logic based on pure software constructs. More particularly, a high-level program language may be used to create a program using only software constructs that is compiled into hardware constructs. Optimizations may be made in the later stages of compilation to retime the circuit, allowing for maximum data flow. The hardware may make run-time decisions with respect to executing programmable logic blocks in parallel. The decisions may be at least partially based on a control flow.Type: GrantFiled: September 22, 2006Date of Patent: June 25, 2013Assignee: Altera CorporationInventor: Paul Metzgen
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Publication number: 20130014095Abstract: A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g., RAM). This facilitates multiple reads during a single clock cycle. Symbol set analysis is used to minimize the size of regions to allow for more efficient use of hardware resources.Type: ApplicationFiled: September 13, 2012Publication date: January 10, 2013Applicant: ALTERA CORPORATIONInventor: Paul Metzgen
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Patent number: 8332831Abstract: A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g., RAM). This facilitates multiple reads during a single clock cycle. Symbol set analysis is used to minimize the size of regions to allow for more efficient use of hardware resources.Type: GrantFiled: January 31, 2008Date of Patent: December 11, 2012Assignee: Altera CorporationInventor: Paul Metzgen
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Patent number: 8214419Abstract: Methods and apparatus are provided for implementing an efficient saturating multiplier associated with addition and subtraction logic. The result of the multiplier is saturated before accumulating. The result of the multiplier can be stored in a result register in unsaturated form. The output of the result register can then be saturated and provided to addition and subtraction logic to allow efficient implementation of a saturating multiplier.Type: GrantFiled: December 30, 2008Date of Patent: July 3, 2012Assignee: Altera CorporationInventor: Paul Metzgen
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Patent number: 8190828Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.Type: GrantFiled: May 13, 2009Date of Patent: May 29, 2012Assignee: Altera CorporationInventors: Roger May, Andrew Draper, Paul Metzgen, Neil Thorne
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Patent number: 8019981Abstract: Methods and apparatus are provided for performing loop execution. Modifier registers are used to hold loop counter values. Modifier register information and program memory address information are included in the loop instruction. When a processor executes a loop instruction, it decodes the instruction, identifies the modifier register, and accesses the register value to determine if the processor will jump back based on the memory address information. The loop execution can incur no clock cycle penalties.Type: GrantFiled: August 12, 2004Date of Patent: September 13, 2011Assignee: Altera CorporationInventor: Paul Metzgen
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Patent number: 8005177Abstract: In order to reduce the crest factor of a signal for power amplification, a windowing function is applied. The windowing function that is applied is a triangular windowing function. The use of this function produces good results when those results are measured in terms of their effect on a transmitted signal in a WCDMA communications system. The filter for performing the triangular windowing function receives the signal, and applies it to a first delay element. The output from the first delay element is applied to a second delay element. An adder forms a weighted sum of the received signal and the signals at the outputs of the first delay element and the second delay element. A first accumulator is connected to receive an input from the adder and provides a first accumulator output, while a second accumulator is connected to receive an input from the first accumulator output and provides a second accumulator output.Type: GrantFiled: August 11, 2009Date of Patent: August 23, 2011Assignee: Altera CorporationInventors: Volker Mauer, Kulwinder Dhanoa, Paul Metzgen
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Patent number: 7930521Abstract: Methods and apparatus are provided for reducing the amount of resources allocated for handling multiplexing in a processor. Characteristics associated with processing blocks are analyzed. Operand restrictions and register groups can be configured to allow the use of more resource efficient multiplexing circuitry in a processor.Type: GrantFiled: June 11, 2008Date of Patent: April 19, 2011Assignee: Altera CorporationInventor: Paul Metzgen
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Patent number: 7586995Abstract: In order to reduce the crest factor of a signal for power amplification, a windowing function is applied. The windowing function that is applied is a triangular windowing function. The use of this function produces good results when those results are measured in terms of their effect on a transmitted signal in a WCDMA communications system. The filter for performing the triangular windowing function receives the signal, and applies it to a first delay element. The output from the first delay element is applied to a second delay element. An adder forms a weighted sum of the received signal and the signals at the outputs of the first delay element and the second delay element. A first accumulator is connected to receive an input from the adder and provides a first accumulator output, while a second accumulator is connected to receive an input from the first accumulator output and provides a second accumulator output.Type: GrantFiled: April 18, 2005Date of Patent: September 8, 2009Assignee: Altera CorporationInventors: Volker Mauer, Kulwinder Dhanoa, Paul Metzgen
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Patent number: 7581088Abstract: Methods and apparatus are provided for optimizing a conditional execution on a processor core. A processor sets a flag based on both the result and the type of an instruction. The flag is used during evaluation of a subsequent instruction to determine if the subsequent instruction should be executed. A semantically overloaded flag can be used to efficiently handle chained logical comparisons.Type: GrantFiled: June 16, 2004Date of Patent: August 25, 2009Assignee: Altera CorporationInventor: Paul Metzgen
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Publication number: 20090172067Abstract: Methods and apparatus are provided for implementing an efficient saturating multiplier associated with addition and subtraction logic. The result of the multiplier is saturated before accumulating. The result of the multiplier can be stored in a result register in unsaturated form. The output of the result register can then be saturated and provided to addition and subtraction logic to allow efficient implementation of a saturating multiplier.Type: ApplicationFiled: December 30, 2008Publication date: July 2, 2009Inventor: Paul Metzgen
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Patent number: 7546424Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.Type: GrantFiled: June 2, 2006Date of Patent: June 9, 2009Assignee: Altera CorporationInventors: Roger May, Andrew Draper, Paul Metzgen, Neil Thorne
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Patent number: 7523421Abstract: Methods and apparatus are provided for reducing the cost of multiplexer circuitry. Electrically equivalent data inputs and corresponding multiplexers can be eliminated from a multiplexer cone. A new multiplexer and new selection circuitry can be added to preserve the logical function of the cone. Such a method can result in substantial cost savings in the multiplexer circuitry, especially when applied to a multiplexer cone bus of relatively large width.Type: GrantFiled: December 22, 2005Date of Patent: April 21, 2009Assignee: Altera CorporationInventors: Dominic J Nancekievill, Paul Metzgen