Patents by Inventor Paul Metzgen
Paul Metzgen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090100122Abstract: Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.Type: ApplicationFiled: November 26, 2008Publication date: April 16, 2009Applicant: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Steven Perry, Paul Metzgen, Nitin Prasad, William Hwang
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Patent number: 7487196Abstract: Methods and apparatus are provided for implementing an efficient saturating multiplier associated with addition and subtraction logic. The result of the multiplier is saturated before accumulating. The result of the multiplier can be stored in a result register in unsaturated form. The output of the result register can then be saturated and provided to addition and subtraction logic to allow efficient implementation of a saturating multiplier.Type: GrantFiled: August 12, 2004Date of Patent: February 3, 2009Assignee: Altera CorporationInventor: Paul Metzgen
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Patent number: 7475221Abstract: Methods and apparatus are provided for performing circular buffer addressing. Upper boundaries, lower boundaries, circular buffer lengths, addresses, and offsets are set to allow circular buffer access efficiency. An addition/subtraction unit is provided to simplify implementation. Comparators are rearranged and in some instances replaced with combined adder/comparator logic units. The additional logic units and the rearrangement allow efficient implementation of circular buffer addressing, particularly on programmable chips.Type: GrantFiled: July 16, 2004Date of Patent: January 6, 2009Assignee: Altera CorporationInventors: Paul Metzgen, Dominic Nancekievill, Tracy Miranda
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Patent number: 7467176Abstract: Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.Type: GrantFiled: February 20, 2004Date of Patent: December 16, 2008Assignee: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Steven Perry, Paul Metzgen, Nitin Prasad, William Hwang
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Patent number: 7441105Abstract: Methods and apparatus are provided for reducing the amount of resources allocated for handling multiplexing in a processor. Characteristics associated with processing blocks are analyzed. Operand restrictions and register groups can be configured to allow the use of more resource efficient multiplexing circuitry in a processor.Type: GrantFiled: June 16, 2004Date of Patent: October 21, 2008Assignee: Altera CorporationInventor: Paul Metzgen
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Patent number: 7437401Abstract: A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.Type: GrantFiled: February 20, 2004Date of Patent: October 14, 2008Assignee: Altera CorporationInventors: Leon Zheng, Martin Langhammer, Steven Perry, Paul Metzgen, Gregory Starr, William Hwang, Kumara Tharmalingam
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Patent number: 7395360Abstract: Methods and apparatus are provided for implementing a bus arbitration priority encoding scheme with fairness. Bus arbitration logic is connected to multiple primary components or devices. The multiple primary components send requests to bus arbitration logic. The bus arbitration logic uses a request vector and an arbitration vector to determine a grant vector. The grant vector indicates what primary component should be allowed bus access.Type: GrantFiled: September 21, 2005Date of Patent: July 1, 2008Assignee: Altera CorporationInventors: Jeffrey Orion Pritchard, Kerry Veenstra, Aaron Ferrucci, Paul Metzgen
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Patent number: 7358767Abstract: Methods and apparatus are provided for implementing efficient multiplexers on a programmable chip using a lookup table. A load logic input line associated with a lookup table having limited input lines is used to augment the number of input lines that can be handled by a particular lookup table. Load logic and a lookup table having four input lines can be used to implement a 3:1 multiplexer having five input lines.Type: GrantFiled: June 16, 2004Date of Patent: April 15, 2008Assignee: Altera CorporationInventors: Paul Metzgen, Dominic Nancekievill
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Patent number: 7358760Abstract: Methods and apparatus are provided for implementing efficient multiplexers on a programmable chip using a lookup table (LUT). A load logic input line associated with a LUT having limited input lines is used to augment the number of input lines that can be handled by a particular LUT. A reset logic input line associated with a LUT is further used to augment the number of input lines. Load logic, reset logic, and a LUT having four input lines can be used to implement a 4:1 multiplexer having seven input lines including four data and three control lines.Type: GrantFiled: November 24, 2004Date of Patent: April 15, 2008Assignee: Altera CorporationInventors: Dominic Nancekievill, Paul Metzgen
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Patent number: 7343594Abstract: A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g., RAM). This facilitates multiple reads during a single clock cycle. Symbol set analysis is used to minimize the size of regions to allow for more efficient use of hardware resources.Type: GrantFiled: July 31, 2002Date of Patent: March 11, 2008Assignee: Altera CorporationInventor: Paul Metzgen
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Patent number: 7257780Abstract: A hardware-to-software compiler is provided that runs an optimization on a circuit implemented in programmable logic. The optimization allows portions of the program implemented by the circuit to be executed via software. A communication interface between the hardware and software is provided that allows for efficient data flow. A communication channel is provided that can be effected as bidirectional using a unidirectional transport medium (e.g., PCI bus). Communication between devices is done through pop interface buffers and push interface buffers on either side of the communication channel.Type: GrantFiled: August 7, 2001Date of Patent: August 14, 2007Assignee: Altera CorporationInventor: Paul Metzgen
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Publication number: 20070169033Abstract: A software-to-hardware compiler is provided that generates hardware constructs in programmable logic based on pure software constructs. More particularly, a high-level program language may be used to create a program using only software constructs that is compiled into hardware constructs. Optimizations may be made in the later stages of compilation to retime the circuit, allowing for maximum data flow. The hardware may make run-time decisions with respect to executing programmable logic blocks in parallel. The decisions may be at least partially based on a control flow.Type: ApplicationFiled: September 22, 2006Publication date: July 19, 2007Inventor: Paul Metzgen
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Patent number: 7219342Abstract: A software-to-hardware compiler is provided that generates hardware constructs in programmable logic based on pure software constructs. More particularly, a high-level program language may be used to create a program using only software constructs that is compiled into hardware constructs. Optimizations may be made in the later stages of compilation to retime the circuit, allowing for maximum data flow. The hardware may make run-time decisions with respect to executing programmable logic blocks in parallel. The decisions may be at least partially based on a control flow.Type: GrantFiled: August 7, 2001Date of Patent: May 15, 2007Assignee: Altera CorporationInventor: Paul Metzgen
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Publication number: 20060288061Abstract: Adder units are used to compare two numbers. A first logic unit receives one or more bits from a first number and the bits from a second number less the least significant bit of that second number. A second logic unit receives one or more bits from the second number and the bits from the first number less the least significant bit of that first number. The logic units generate, based on the logic values (bits) input into the logic units, logic values and output those values to an adder unit. Using these values, in addition to a “Carry In” value, the adder unit generates an output. The output is at least partially determinative of whether the second number is greater than the first number. Comparators designed in accordance with the present invention incur less delay (i.e., are faster) and require less inputs into logic look-up tables than prior comparators.Type: ApplicationFiled: June 20, 2005Publication date: December 21, 2006Applicant: Altera CorporationInventors: Dominic Nancekievill, Paul Metzgen
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Patent number: 7096324Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.Type: GrantFiled: June 12, 2001Date of Patent: August 22, 2006Assignee: Altera CorporationInventors: Roger May, Andrew Draper, Paul Metzgen, Neil Thorne
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Patent number: 7002370Abstract: A multiplexer is configured on a programmable logic device using a plurality of four-input look-up tables chained together. The required number of look-up tables is about one-half the number of inputs of the multiplexer. For an even number of inputs, the number of look-up tables preferably is exactly one-half the number of inputs, while for an odd number of inputs, the number of look-up tables preferably is one-half the number of inputs, plus one-half. The number of control inputs preferably is one more than the number of look-up tables. Preferably, for any one input being a given logic state, and further selected by the one extra input (beyond the number of look-up tables), any particular output may be asserted.Type: GrantFiled: December 4, 2003Date of Patent: February 21, 2006Assignee: Altera CorporationInventors: Paul Metzgen, Dominic Nancekievill
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Publication number: 20050187999Abstract: Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.Type: ApplicationFiled: February 20, 2004Publication date: August 25, 2005Inventors: Leon Zheng, Martin Langhammer, Steven Perry, Paul Metzgen, Nitin Prasad, William Hwang
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Publication number: 20050187998Abstract: A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.Type: ApplicationFiled: February 20, 2004Publication date: August 25, 2005Inventors: Leon Zheng, Martin Langhammer, Steven Perry, Paul Metzgen, Gregory Starr, William Hwang, Kumara Tharmalingam
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Publication number: 20020124238Abstract: A software-to-hardware compiler is provided that generates hardware constructs in programmable logic based on pure software constructs. More particularly, a high-level program language may be used to create a program using only software constructs that is compiled into hardware constructs. Optimizations may be made in the later stages of compilation to retime the circuit, allowing for maximum data flow. The hardware may make run-time decisions with respect to executing programmable logic blocks in parallel. The decisions may be at least partially based on a control flow.Type: ApplicationFiled: August 7, 2001Publication date: September 5, 2002Inventor: Paul Metzgen
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Publication number: 20020100032Abstract: A hardware-to-software compiler is provided that runs an optimization on a circuit implemented in programmable logic. The optimization allows portions of the program implemented by the circuit to be executed via software. A communication interface between the hardware and software is provided that allows for efficient data flow. A communication channel is provided that can be effected as bidirectional using a unidirectional transport medium (e.g., PCI bus). Communication between devices is done through pop interface buffers and push interface buffers on either side of the communication channel.Type: ApplicationFiled: August 7, 2001Publication date: July 25, 2002Inventor: Paul Metzgen