Patents by Inventor Paul R. Walling
Paul R. Walling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10956649Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.Type: GrantFiled: August 22, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anson J. Call, Francesco Preda, Paul R. Walling
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Patent number: 10949600Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.Type: GrantFiled: August 13, 2019Date of Patent: March 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jean Audet, Franklin M. Baez, Jason L. Frankel, Paul R. Walling
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Patent number: 10546096Abstract: Embodiments of the invention include methods, systems, and computer program products for checking semiconductor package via proximity rules. Aspects of the invention include receiving, by a processor, the via proximity rules and a semiconductor package design including one or more package layers and a plurality of vias. Each via is mapped to a cell in a three-dimensional array and a via stack including each via is identified. The via stacks are checked against the via proximity rules. A list of via stacks which did not satisfy the via proximity rules is displayed on a user interface.Type: GrantFiled: September 29, 2017Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anson J. Call, Paul R. Walling
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Publication number: 20190377850Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.Type: ApplicationFiled: August 22, 2019Publication date: December 12, 2019Inventors: Anson J. Call, Francesco Preda, Paul R. Walling
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Publication number: 20190362049Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.Type: ApplicationFiled: August 13, 2019Publication date: November 28, 2019Inventors: Jean Audet, Franklin M. Baez, Jason L. Frankel, Paul R. Walling
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Patent number: 10423752Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.Type: GrantFiled: September 29, 2017Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anson J. Call, Francesco Preda, Paul R. Walling
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Patent number: 10423751Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.Type: GrantFiled: September 29, 2017Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jean Audet, Franklin M. Baez, Jason L. Frankel, Paul R. Walling
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Patent number: 10375820Abstract: A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.Type: GrantFiled: March 22, 2018Date of Patent: August 6, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jinwoo Choi, Sungjun Chun, Jason L. Frankel, Paul R. Walling, Roger D. Weekly
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Publication number: 20190102504Abstract: Embodiments of the invention include methods, systems, and computer program products for checking semiconductor package via proximity rules. Aspects of the invention include receiving, by a processor, the via proximity rules and a semiconductor package design including one or more package layers and a plurality of vias. Each via is mapped to a cell in a three-dimensional array and a via stack including each via is identified. The via stacks are checked against the via proximity rules. A list of via stacks which did not satisfy the via proximity rules is displayed on a user interface.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Anson J. Call, Paul R. Walling
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Publication number: 20190102505Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Jean Audet, Franklin M. Baez, Jason L. Frankel, Paul R. Walling
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Publication number: 20190102506Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Anson J. Call, Francesco Preda, Paul R. Walling
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Publication number: 20180213636Abstract: A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.Type: ApplicationFiled: March 22, 2018Publication date: July 26, 2018Inventors: JINWOO CHOI, SUNGJUN CHUN, JASON L. FRANKEL, PAUL R. WALLING, ROGER D. WEEKLY
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Patent number: 9955567Abstract: A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.Type: GrantFiled: July 27, 2014Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jinwoo Choi, Sungjun Chun, Jason L. Frankel, Paul R. Walling, Roger D. Weekly
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Patent number: 8927879Abstract: A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained.Type: GrantFiled: November 22, 2010Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Jinwoo Choi, Sungjun Chun, Jason L. Frankel, Paul R. Walling, Roger D. Weekly
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Publication number: 20140331482Abstract: A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.Type: ApplicationFiled: July 27, 2014Publication date: November 13, 2014Inventors: JINWOO CHOI, SUNGJUN CHUN, JASON L. FRANKEL, PAUL R. WALLING, ROGER D. WEEKLY
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Patent number: 8756546Abstract: A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.Type: GrantFiled: July 25, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Erwin B. Cohen, Mark C. H. Lamorey, Marek A. Orlowski, Douglas O. Powell, David L. Questad, David B. Stone, Paul R. Walling
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Publication number: 20140033148Abstract: A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.Type: ApplicationFiled: July 25, 2012Publication date: January 30, 2014Applicant: International Business Machines CorporationInventors: Erwin B. Cohen, Mark C.H. Lamorey, Marek A. Orlowski, Douglas O. Powell, David L. Questad, David B. Stone, Paul R. Walling
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Publication number: 20120125677Abstract: A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained.Type: ApplicationFiled: November 22, 2010Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jinwoo Choi, Sungjun Chun, Jason L. Frankel, Paul R. Walling, Roger D. Weekly
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Patent number: 7325213Abstract: A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substrate. The subset substrate has identical internal net lists as the portion of the master substrate. The subset substrate is adapted to accommodate a smaller chip than the master substrate. The master substrate is the largest substrate in the system. The invention also prepares a system of chip packages. The invention selects a master substrate and then selects a subset substrate of the master substrate.Type: GrantFiled: June 17, 2005Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Harsaran S. Bhatia, Marie S. Cole, Michael S. Cranmer, Jason Lee Frankel, Eric Kline, Kenneth A. Papae, Paul R. Walling
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Patent number: 7096451Abstract: A method, system and program product implementing storage of a (power or ground) mesh plane file using a multiple line shape, possibly with the storage of lines also, to reduce file size. In addition, the invention implements an activate-substantial-portion-and-remove technique to generate mesh planes rather than the conventional additive approach, which improves the speed of designing the IC carriers. A resulting mesh plane design file may be as much as half the size of a file generated using the conventional line-by-line and storage approaches.Type: GrantFiled: September 9, 2003Date of Patent: August 22, 2006Assignee: International Business Machines CorporationInventors: Alice L. Donaldson, Jason L. Frankel, John A. Ludwig, Kenneth A. Papae, Rafael Perez-Acevedo, C. Timothy Ryan, Paul R. Walling