Abstract: A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer.

Abstract: A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer.

Abstract: A method for designing a multilayer module for a semiconductor package and for determining connections within a multilayer module having input-output (IO) contacts in a first array defined by first array information. A chip within the module has C4 contacts arranged in a second array defined by second array information. The connections are intermediate pairs of the IO contacts and the C4 contacts among a plurality of layers. The method comprises the steps of storing the first and second array information in storage; identifying connection paths in a layer between the pairs according to a selection algorithm using the first and second array information; identifying crossing paths; swapping either the C4 or IO contacts of selected crossing paths; identifying paths being blocked by another connection path to identify a need for a next layer to complete the blocked connection paths; repeating the method for subsequent layers for a predetermined number of iterations or until all connection paths are defined.