Patents by Inventor Paul Ranucci

Paul Ranucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7554152
    Abstract: The present invention provides a versatile system for producing sense transistors having optimized thermal and parametric matching with an associated power transistor. A power transistor is formed, having a plurality of alternating source and drain structures, with a plurality of gate structures interposed there between. At a desired location within the power transistor—which may be in a central location, or symmetrically distributed—one or more sense transistors are formed from an isolated portion of either a drain or source structure.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: June 30, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Paul Ranucci, Robert Labicane
  • Patent number: 7164259
    Abstract: An apparatus and method for producing an output reference voltage is provided. A voltage divider is configured to provide the output reference voltage from a bandgap reference voltage. The bandgap reference voltage is applied across a biased portion of the voltage divider. Additionally, a second-order temperature coefficient (TC) of the impedance of a controllable portion of the voltage divider is adjusted in response to a second-order trim signal. The first and zeroth order TCs of the controllable portion of the voltage divider are substantially independent of the second-order trim signal. In one embodiment, the controllable portion includes a resistor digital-to-analog converter (DAC) that is responsive to the second-order trim signal. The resistor DAC includes at least two different types of resistors. The second-order TCs of the two different types of resistors are substantially different.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: January 16, 2007
    Assignee: National Semiconductor Corporation
    Inventors: David James Megaw, Paul Ranucci
  • Patent number: 6781450
    Abstract: The present invention is related to glitch reduction of the output of an auto-zero amplifier. The auto-zero amplifier may be used in a voltage regulator, and the glitch reduction in the auto-zero amplifier will result in reduced output ripple. The auto-zero amplifier stores an input offset during an auto-zero phase, so that the input offset can be corrected during an amplification phase. During the amplification phase, the gate-drain voltage of a first transistor is sampled onto a capacitor. During the auto-zero phase, the capacitor is used to maintain the same voltage across the gate-drain voltage of the first transistor that was present during the amplification phase. The capacitor maintains the gate-drain voltage during the auto-zero phase in order to compensate for the large step in voltage that would otherwise occur.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: August 24, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Mark J. Mercer, Paul Ranucci