Abstract: The invention is a dynamic random access memory (DRAM) device having an electronic test key fabricated on board and is a method for testing the DRAM. The electronic test key generates a signal which effects a variation in a period of an internal control signal to stress the DRAM during a test mode.

Abstract: An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. A clock signal is provided to synchronize the burst operations. The clock signal is independent of an address latch signal used to latch an external address.

Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

Abstract: A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array bit lines and data input/output connections are distributed around the memory to increase speed. Multiplexed latch circuitry is provided which incorporates separate data paths for both data read and write operations.

Abstract: A dynamic integrated circuit memory is described which has memory cells arranged in rows. The memory rows are selectively accessible using an addressing circuit and local phase lines. Distributed local phase driver circuits are used to drive the local phase lines to a pumped voltage which are coupled to the gate of a memory cell access transistor. Addressing circuitry is provided to selectively address the distributed local phase driver circuits.

Abstract: An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inoperable it is electrically isolated from the remaining circuitry on the integrated circuit so that it cannot interfere with the normal operation of the remaining circuitry. Defects such as power to ground shorts in a subarray which would have previously been catastrophic can be electrically isolated allowing the remaining functional subarrays to be utilized. Integrated circuit repair by isolation of inoperative elements eliminates the current draw and other performance degradations that have previously been associated with integrated circuits with defects repaired through the incorporation of redundant elements alone.

Abstract: A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added to a standard laser fuse structure such that it intersects the fuses and the number of available fuses is doubled.

Abstract: A memory circuit is described which increases the density of memory cells by including a reference circuit. The memory circuit has an open digit line architecture where sense amplifiers use two digit lines to sense data stored in the memory cells. One of the digit lines is used as a reference while the other digit line is active. A reference circuit is described which can be used to replace one of the digit lines connected to the sense amplifier circuit. The reference circuit models the electrical characteristics of a digit line by including a capacitor and a transistor, each sized to match the characteristics of a digit line.

Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

Abstract: In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynamic random access memory (DRAM) which uses a selectively blowable anti-fuse to disable a redundant element which was previously programmed to replace a defective primary element. The disclosure describes a method for permanently cancelling the defective redundant element and replacing the defective redundant element with another redundant element.

Abstract: A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.

Abstract: An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additioned memory addresses. A clock signed is provided to synchronize the burst operations. The clock signed is independent of an address latch signal used to latch an external address.

Abstract: An integrated circuit memory device has two banks of NAND structured memory cells and a clock input for synchronously latching control, address and data signals. Time delays of sequentially accessing and restoring memory bits in the NAND structure are masked through the use of the dual bank architecture and synchronous timing. The NAND structured memory cells provide an extremely dense memory array for a high capacity memory device. The input clock signal driving a synchronous word line generator provides a simplified high speed access to the array. A set of random access storage registers temporarily store data from the array and provide high speed page access to an entire page of data from each bank of the memory. The ability to access one bank while simultaneously opening or closing a row in the other bank allows for an unlimited number of high speed sequential data accesses.

Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

Abstract: A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added to a standard laser fuse structure such that it intersects the fuses and the number of available fuses is doubled.

Abstract: A memory circuit is described which increases the density of memory cells by including a reference circuit. The memory circuit has an open digit line architecture where sense amplifiers use two digit lines to sense data stored in the memory cells. One of the digit lines is used as a reference while the other digit line is active. A reference circuit is described which can be used to replace one of the digit lines connected to the sense amplifier circuit. The reference circuit models the electrical characteristics of a digit line by including a capacitor and a transistor, each sized to match the characteristics of a digit line.

Abstract: A dynamic integrated circuit memory is described which has memory cells arranged in rows. The memory rows are selectively accessible using an addressing circuit and local phase lines. Distributed local phase driver circuits are used to drive the local phase lines to a pumped voltage which are coupled to the gate of a memory cell access transistor. Addressing circuitry is provided to selectively address the distributed local phase driver circuits.

Abstract: A power supply for an integrated circuit has a piecewise linear operating characteristic for improved integrated circuit testing and screening. In an integrated circuit that receives an externally applied power signal, designated V.sub.CCX, and includes a power supply for generating an internal operating voltage, designated V.sub.CCR, an on-chip power supply circuit provides V.sub.CCR as a piecewise linear function of V.sub.CCX. In a first segment of such a function, V.sub.CCR approximates V.sub.CCX for efficient low voltage operations. In a second segment, used for normal operations of the integrated circuit, V.sub.CCR rises gradually with V.sub.CCX so that test results at the edges of the segment can be guaranteed with a margin for measurement tolerance, process variation, and derating. In a third segment, V.sub.CCR follows below V.sub.CCX at a predetermined constant offset. Transitions between segments are smooth due to nonlinear devices used in the power supply circuitry.

Abstract: The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of the row decoder. Power is conserved since the serial nodes are passively pulled to the supply potential through the precharge devices. The invention increases speed and provides error free wordline selection.

Abstract: A method for maintaining optimum biasing voltage and standby current levels in a dynamic random access memory array, in which row-to-column shorts have been repaired by redirecting the addresses of shorted rows and columns to spare rows and columns. The method partly consists of placing a current limiting device in series with the bias voltage generator output and the nodes between the equilibration transistors of small groups of digit line pairs. The current limiting devices may be either long-L transistors that are in an always-on state, or they may be merely resistive elements, such as strips of lightly-doped polysilicon. The invention effectively isolates the effect of row-to-column shorts in a portion of a DRAM array from the remainder of the array. All digit line pairs tied to a single current limiting device are replaced as a unit if any one or more of the digit lines among the tied pairs is shorted to a word line.