Abstract: A method and apparatus for optimizing the speed path of a memory access operation in a synchronous depending upon the present latency period for the synchronous DRAM. The improved memory device compensates the time between row address latching and column address latching (tRCD) by delaying the presentment of the column address to compensate tRCD from the time available for column address latching to valid data-out (tAA) when tRCD is the critical parameter. Optimization circuitry reduces the amount of time available for tAA and "shifts" it to the more critical parameter tRCD, enabling the optimization or reduction of the time allocated for tRCD by compensating tRCD with the extra time available for tAA. Thus, the memory access optimization circuitry enables an optimization or reduction in the total memory access time by compensating the optimized tRCD with the extra time available for tAA.

Abstract: A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The system comprises a dedicated match circuit for each redundant row in a given section. The match circuit analyzes incoming address information to determine whether the address corresponds to a memory location in a specific defective row in any one of a number of sub-array blocks within the section. When such a critical address is detected, the match circuit activates circuitry which inhibits access to the defective row and enables access to its dedicated redundant row.

Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

Abstract: A memory integrated circuit chip of a predefined circuit topology has an on-chip topology logic driver. The topology logic driver selectively inverts data being written to and read from addressed memory cells in the memory IC based upon location of the addressed memory cells in the circuit topology of the memory array. The topology logic driver is preferably a logic circuit that embodies a boolean function defining the circuit topology. A method for testing and producing such memory ICs is also described.

Abstract: A simple, low-power sense circuit is disclosed that accurately tracks charge transfer between the capacitor of a dynamic random access memory cell and its associated digit line. The circuit, which is preferably located in the peripheral circuitry, employs a model access transistor to charge a pull-up node that is coupled to ground through a capacitor which simulates digit line capacitance. The pull-up node is coupled to the gate of a N-channel field-effect output transistor. When voltage on the node reaches the threshold voltage of the output transistor, the output transistor begins to turn on. The output from the output transistor (in this case, ground potential) is fed back to the gate of a P-channel device which couples the node to V.sub.CC. The P-channel device is used to pull up the node to V.sub.CC rapidly once the trip point (i.e., the threshold voltage) of the N-channel output transistor is reached.

Abstract: A programmable logic device (PLD) with an output macrocell circuit is disclosed. Specifically, there is a macrocell having an exclusive logic signal feedback line and an exclusive external input signal line both feeding into the input of the PLD. Exactly, this PLD can disable the I/O pad and still have an internal feedback to its logic circuitry.

Abstract: To enhance the speed at which dynamic random access memories are refreshed, each sensing amplifier is provided with a clamping transistor. The clamping transistor is connected to a preselected voltage source. The clamping transistor prevents the voltage on the low-going bit line from falling to circuit ground by clamping the voltage on the low-going bit line to the preselected voltage.

Abstract: There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.

Abstract: A DRAM or VRAM integrated circuit memory of the divided bit line design includes a first bit line pair divided into a first pair of bit line halves and a second pair of bit line halves, and second bit line pair divided into a third pair of bit line halves and a fourth pair of bit line halves. A row decoder addresses a row associated with the first pair of bit line halves during a first time period, addresses a row associated with the second pair of bit line halves in a second time period, addresses a row associated with the third pair of bit line halves in the first time period, and addresses a row associated with the fourth pair of bit line halves in the second time period. The access topology is thus asymmetric with respect to a column decoder connected to the second and third pairs of bit line halves.

Abstract: The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The driving device is electrically interposed between the wordline and a reference node. The invention provides low power operation, and provides reliable wordline selection for circuits having supply potentials less than 5 volts.

Abstract: The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of the row decoder. Power is conserved since the serial nodes are passively pulled to the supply potential through the precharge devices. The invention increases speed and provides error free wordline selection.

Abstract: A programmable logic device (PLD) is disclosed, which can efficiently, in a realestate sense, emulate a Mealy state machine. Specifically, there is a PLD which has macrocells which accept signals from two separate logical OR arrays. Where the first array and macrocell produces a latched output signal and the second array and macrocell circuit produces a non-latched output signal.

Abstract: There is a DRAM which provides for a faster non-accessed memory cell ones voltage level refresh or restore process. Specifically, the DRAM does not shut down a digit line's voltage pull-up circuitry (PSA) during a write operation. By leaving on the PSA, the digit lines being pulled to a ones voltage level will continue to be pulled up during the write operation. Thus, a non-accessed digit line will reach the ones voltage level in a shorter time than if the PSA were turned off during the write operation.

Abstract: A CMOS logic cell, which may be readily arrayed to construct fast, zero-power programmable array logic (PAL) devices or field-programmable logic array (FPLAs) is disclosed. The cell is constructed from first and second pairs of P-channel insulated-gate field effect transistors (IGFETs), and first and second pairs of N-channel IGFETs. Each pair of P-channel IGFETS is connected in series between an output node and V.sub.cc, while each pair of N-channel IGFETS is connected in series between the output node and V.sub.ss. The gate of one transistor of the first. P-channel IGFET pair is connected to the output of a first memory cell, while the gate of the other transistor of the same pair is connected to an input signal I; the gate of one transistor of the second P-channel IGFET pair is connected to the output of a second memory cell, while the gate of the other transistor of the same pair is connected to signal I* (the complement of input signal I).

Abstract: A method for maintaining optimum biasing voltage and standby current levels in a dynamic random access memory array, in which row-to-column shorts have been repaired by redirecting the addresses of shorted rows and columns to spare rows and columns. The method partly consists of placing a current limiting device in series with the bias voltage generator output and the nodes between the equilibration transistors of small groups of digit line pairs. The current limiting devices may be either long-L transistors that are in an always-on state, or they may be merely resistive elements, such as strips of lightly-doped polysilicon. The invention effectively isolates the effect of row-to-column shorts in a portion of a DRAM array from the remainder of the array. All digit line pairs tied to a single current limiting device are replaced as a unit if any one or more of the digit lines among the tied pairs is shorted to a word line.

Abstract: A programmable logic device (PLD) is disclosed for finding a sum of products or other logic equations. Specifically, there is a PLD which has: 1) a programmable logical AND and programmable logical OR arrays/matrices, similar to a field programmable logic array; and 2) the fully programmable OR array has an optimized signal speed path and non-optimized signal speed path.

Abstract: A programmable logic device (PLD) is disclosed which can efficiently, in a real estate sense, emulate a Mealy state machine. Specifically, there is a PLD which has: (1) a programmable logical AND and two programmable logical OR arrays, similar to a field programmable logic array; and (2) one of the two fully programmable OR array generates a next state of the circuit and the second OR array generates an output responsive to both the inputs and the current state.

Abstract: This disclosure describes a nonvolatile zero-power memory cell circuit constructed from anti-fuses operable at less than full power supply voltage, and which provides full CMOS output voltage levels. The cell comprises a programmable node which is connected to a high voltage line (which during normal operation is at a potential of approximately V.sub.cc /2) via a first antifuse and to a low voltage line (which during normal operation is at ground potential) via a second antifuse. The programmable node is connectable to ground via a field-effect transistor which is controlled by a programming signal. The programmable node may be permanently connected to the high-voltage line by activating the programming signal and raising the voltage on that line to a voltage that is sufficiently high to cause the dielectric of the first antifuse to short.