Patents by Inventor Paul Santeler
Paul Santeler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7409581Abstract: A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.Type: GrantFiled: August 5, 2002Date of Patent: August 5, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Paul A. Santeler, Kenneth A. Jansen, Sompong P. Olarig
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Patent number: 7116241Abstract: A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.Type: GrantFiled: May 14, 2003Date of Patent: October 3, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christian H. Post, George D. Megason, Brett D. Roscoe, Paul Santeler, John M. MacLaren, John E. Larson, Jeffery Galloway, Siamak Tavallaei, Tim W. Majni, Robert Allan Lester, Anisha Anand, Eric Rose
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Patent number: 6975241Abstract: A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.Type: GrantFiled: May 14, 2003Date of Patent: December 13, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christian H. Post, George D. Megason, Brett D. Roscoe, Paul Santeler, John M. MacLaren, John E. Larson, Jeffery Galloway, Siamak Tavallaei, Tim W. Majni, Robert Allan Lester, Anisha Anand, Eric Rose
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Patent number: 6785835Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The system supports DIMMs having X4 and X8 configurations. The system also transitions between various states, including a redundant state and a non-redundant state, to facilitate “hot-plug” capabilities utilizing its removable memory cartridges.Type: GrantFiled: January 25, 2001Date of Patent: August 31, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: John M. MacLaren, Paul Santeler, Kenneth A. Jansen, Sompong P. Olarig, Robert A. Lester, Patrick L. Ferguson, John E. Larson, Jerome J. Johnson, Gary J. Piccirillo
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Patent number: 6747563Abstract: A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.Type: GrantFiled: May 14, 2003Date of Patent: June 8, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christian H. Post, George D. Megason, Brett D. Roscoe, Paul Santeler, John M. MacLaren, John E. Larson, Jeffery Galloway, Siamak Tavallaei, Tim W. Majni, Robert Allan Lester, Anisha Anand, Eric Rose
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Publication number: 20030201902Abstract: A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.Type: ApplicationFiled: May 14, 2003Publication date: October 30, 2003Inventors: Christian H. Post, George D. Megason, Brett D. Roscoe, Paul Santeler, John M. MacLaren, John E. Larson, Jeffery Galloway, Siamak Tavallaei, Tim W. Majni, Robert Allan Lester, Anisha Anand, Eric Rose
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Publication number: 20030193402Abstract: A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.Type: ApplicationFiled: May 14, 2003Publication date: October 16, 2003Inventors: Christian H. Post, George D. Megason, Brett D. Roscoe, Paul Santeler, John M. MacLaren, John E. Larson, Jeffery Galloway, Siamak Tavallaei, Tim W. Majni, Robert Allan Lester, Anisha Anand, Eric Rose
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Publication number: 20030193403Abstract: A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.Type: ApplicationFiled: May 14, 2003Publication date: October 16, 2003Inventors: Christian H. Post, George D. Megason, Brett D. Roscoe, Paul Santeler, John M. MacLaren, John E. Larson, Jeffery Galloway, Siamak Tavallaei, Tim W. Majni, Robert Allan Lester, Anisha Anand, Eric Rose
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Patent number: 6608564Abstract: A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.Type: GrantFiled: January 25, 2001Date of Patent: August 19, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christian H. Post, George D. Megason, Brett D. Roscoe, Paul Santeler, John M. MacLaren, John E. Larson, Jeffery Galloway, Siamak Tavallaei, Tim W. Majni, Robert Allan Lester, Anisha Anand, Eric Rose
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Publication number: 20020194530Abstract: A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.Type: ApplicationFiled: August 5, 2002Publication date: December 19, 2002Inventors: Paul A. Santeler, Kenneth A. Jansen, Sompong P. Olarig
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Patent number: 6430702Abstract: A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.Type: GrantFiled: November 15, 2000Date of Patent: August 6, 2002Assignee: Compaq Computer CorporationInventors: Paul A. Santeler, Kenneth A. Jansen, Sompong P. Olarig
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Publication number: 20020010835Abstract: A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.Type: ApplicationFiled: January 25, 2001Publication date: January 24, 2002Inventors: Christian H. Post, George D. Megason, Brett D. Roscoe, Paul Santeler, John M. MacLaren, John E. Larson, Jeffery Galloway, Siamak Tavallaei, Tim W. Majni, Robert Allan Lester, Anisha Anand, Eric Rose
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Publication number: 20010039632Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The system supports DIMMs having X4 and X8 configurations. The system also transitions between various states, including a redundant state and a non-redundant state, to facilitate “hot-plug” capabilities utilizing its removable memory cartridges.Type: ApplicationFiled: January 25, 2001Publication date: November 8, 2001Inventors: John M. MacLaren, Paul Santeler, Kenneth A. Jansen, Sompong P. Olarig, Robert A. Lester, Patrick L. Ferguson, John E. Larson, Jerome J. Johnson, Gary J. Piccirillo
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Patent number: 6223301Abstract: A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.Type: GrantFiled: September 30, 1997Date of Patent: April 24, 2001Assignee: Compaq Computer CorporationInventors: Paul A. Santeler, Kenneth A. Jansen, Sompong P. Olarig
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Patent number: 6098132Abstract: A computer system includes a memory bus, a connector and a controller. The connector is configured to receive a memory module and prevent removal of the memory module from the connector in a first state. The connector allows removal of the memory module from the connector in a second state. The controller is configured to change a connection status between the connector and the memory bus in response to the connector changing from one of the states to the other state. A central processing unit of the computer system is configured to use the memory bus to store data in the memory module.Type: GrantFiled: September 30, 1997Date of Patent: August 1, 2000Assignee: Compaq Computer CorporationInventors: Sompong P. Olarig, Kenneth A. Jansen, Paul A. Santeler
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Patent number: 5986880Abstract: The cage-supported hard disk drives in a computer server system are coupled to connectors on the cage back plane circuit boards and are controlled by a pair of array controller cards which are hot-plug connected in a redundant manner on the system I/O board using a pair of connectors mounted on the I/O board, each connector having first and second sets of electrical contacts thereon. Connector edge portions of the array controller cards are plugged into the I/O board connectors and have first and second sets of electrical contacts that engage the corresponding first and second sets of electrical contacts on their associated I/O board connectors.Type: GrantFiled: June 16, 1997Date of Patent: November 16, 1999Assignee: Compaq Computer CorporationInventors: Paul A. Santeler, Reza M. Bacchus, Michael L. Sabotta
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Patent number: 5652856Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller takes advantage of different speed memory devices by operating each memory device at optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine has completed its function, it notifies a related state machine that it can now proceed and thereafter waits for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks.Type: GrantFiled: March 5, 1996Date of Patent: July 29, 1997Assignee: Compaq Computer CorporationInventors: Paul A. Santeler, Gary W. Thome
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Patent number: 5651130Abstract: A memory controller dynamically predicts whether a next memory cycle which is not yet available will result in a page miss or page hit condition. RAS lines are selectively precharged if the next memory cycle is predicted to be a page miss. The memory controller keeps track of various combinations of types of cycles when a type of memory cycle is followed by a type of non-memory pending cycle. For each such combination, the memory controller determines the percentage of combinations which result in a page hit on the next memory cycle. Using this history, the memory controller selectively precharges the RAS lines when a certain combination of types of cycles indicates a percentage of hits is below a predicted threshold. If a number of page hits exceeds the predicted threshold, precharging is not performed.Type: GrantFiled: October 17, 1995Date of Patent: July 22, 1997Assignee: Compaq Computer CorporationInventors: Lee B. Hinkle, Gary W. Thome, Paul A. Santeler, David R. Wooten, John A. Landry
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Patent number: 5586286Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller takes advantages of different speed memory devices by operating each memory device at optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine has completed its function, it notifies a related state machine that it can now proceed and thereafter waits for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks.Type: GrantFiled: March 13, 1995Date of Patent: December 17, 1996Assignee: Compaq Computer CorporationInventors: Paul A. Santeler, Gary W. Thome
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Patent number: 5537555Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine completes its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks.Type: GrantFiled: March 22, 1993Date of Patent: July 16, 1996Assignee: Compaq Computer CorporationInventors: John A. Landry, Gary W. Thome, Paul A. Santeler, Randy M. Bonella, Michael J. Collins