Abstract: An apparatus which converts burst mode bus cycles into single cycle mode cycles and converts separate address and data strobe signals into a single address strobe in a computer system. The apparatus also receives an address strobe signal, a number of address signals and the length of the burst when a device begins a burst cycle. After the first cycle of the burst transfer is complete, the apparatus initiates each subsequent cycle comprising the burst transfer by incrementing the address signals and providing additional address strobe signals until the burst is complete. The logic also facilitates address pipelining by monitoring a next address signal generated by the device. The apparatus monitors the separate address strobe and data strobe signals and generates the single address strobe signal on the next clock cycle after the address and data strobe signals are asserted.

Abstract: A computer system that flushes an internal cache in the microprocessor and an external cache to insure cache coherency. The computer system will flush the caches when a write command is directed to those specific portions that are write protected. The microprocessor is placed in a hold state before the flushing process is initiated. The cache memories are then cleared. Thus the microprocessor will not be able to read the incoherent information stored in the cache and yet data obtained during read operations can be cached for performance increase.

Abstract: An apparatus which receives locking signals from a first device and provides a lengthened version of certain of these signals to a second device. The apparatus stretches the locking signal provided to ensure that the signal remains valid throughout the entire locked sequence. The apparatus also indicates when arbitration windows are available between back-to-back locked cycles, i.e. when it is okay to relinquish control of the host bus to a requesting bus master or device. The apparatus monitors cache controller activity and notifies arbitration logic when the last write cycle of a read-modify-write sequence or multiple transfer write cycle begins. When the cycle completes, the arbitration logic releases the bus, thus providing an arbitration window for other requesting bus masters and devices. In this manner, overlock conditions which block bus masters from obtaining control of the bus are prevented from occurring.

Abstract: An electrical system wherein the electrical conductive traces on the circuit boards are routed to achieve a balanced net to reduce noise caused by transmission line reflections. A trace is routed from the source terminal of the net to a balanced junction wherein if there are an odd number of load terminals, or loads, the balanced junction is located at one of the loads. The remaining loads are grouped into branches wherein each branch includes an equal number of loads. A trace is routed between each of the loads of each branch to serially connect the loads of each branch together, or, a trace is routed from a center one of the branch loads to each of the remaining branch loads, forming subbranches. In an alternate embodiment, a balanced subbranch is developed. The balanced load is connected to a pseudo-balanced load, which further receives an equal number of branches. The pseudo-balanced load is then connected to another pseudo-balanced load, which may also receive an equal number of branches.