Abstract: High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips can be used to connect other I/O locations, resulting in decreased impedance between the chips. Additional apparatus, systems, and methods are disclosed.

Abstract: A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components.

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

Abstract: Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Abstract: High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips can be used to connect other I/O locations, resulting in decreased impedance between the chips. Additional apparatus, systems, and methods are disclosed.

Abstract: High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips can be used to connect other I/O locations, resulting in decreased impedance between the chips. Additional apparatus, systems, and methods are disclosed.

Abstract: A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components.

Abstract: A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components.

Abstract: High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips can be used to connect other I/O locations, resulting in decreased impedance between the chips. Additional apparatus, systems, and methods are disclosed.

Abstract: High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips can be used to connect other I/O locations, resulting in decreased impedance between the chips. Additional apparatus, systems, and methods are disclosed.

Abstract: Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of the first signal; an output circuit configured to provide a second signal based on the output signal, the second signal having a cycle time different from a cycle time of the output signal; and a controller configured to adjust the delay to control a timing relationship between the first signal and the second signal. Other embodiments are described and claimed.

Abstract: Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of the first signal; an output circuit configured to provide a second signal based on the output signal, the second signal having a cycle time different from a cycle time of the output signal; and a controller configured to adjust the delay to control a timing relationship between the first signal and the second signal. Other embodiments are described and claimed.

Abstract: An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to the supply voltages is affected by the magnitude of at least one of the supply voltages. The output buffer is driven by a pre-driver coupling first and second control signals to the first and second MOSFET transistors, respectively. The pre-driver adjusts the delay between generating one of the control signals to turn off the MOSFET transistor and generating the other of the control signals to turn on the other MOSFET transistor as a function of the supply voltage magnitude to make the slew rate of the resulting transition substantially insensitive to variations in power supply voltage.

Abstract: Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment, the configuration includes a substrate with a recess, a first die carried by the substrate wherein the die substantially covers the recess, and a logic component carried by the die in a location exposed by the recess. The logic component can be substantially coplanar with the substrate. The die is electrically connected to a terminal on a one side of the substrate, and the logic component is electrically connected to a terminal on an opposite side of the substrate.

Abstract: Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of the first signal; an output circuit configured to provide a second signal based on the output signal, the second signal having a cycle time different from a cycle time of the output signal; and a controller configured to adjust the delay to control a timing relationship between the first signal and the second signal. Other embodiments are described and claimed.

Abstract: High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips can be used to connect other I/O locations, resulting in decreased impedance between the chips. Additional apparatus, systems, and methods are disclosed.

Abstract: A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components.

Abstract: An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to the supply voltages is affected by the magnitude of at least one of the supply voltages. The output buffer is driven by a pre-driver coupling first and second control signals to the first and second MOSFET transistors, respectively. The pre-driver adjusts the delay between generating one of the control signals to turn off the MOSFET transistor and generating the other of the control signals to turn on the other MOSFET transistor as a function of the supply voltage magnitude to make the slew rate of the resulting transition substantially insensitive to variations in power supply voltage.

Abstract: A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components.