Abstract: Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of the first signal; an output circuit configured to provide a second signal based on the output signal, the second signal having a cycle time different from a cycle time of the output signal; and a controller configured to adjust the delay to control a timing relationship between the first signal and the second signal. Other embodiments are described and claimed.

Abstract: An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to the supply voltages is affected by the magnitude of at least one of the supply voltages. The output buffer is driven by a pre-driver coupling first and second control signals to the first and second MOSFET transistors, respectively. The pre-driver adjusts the delay between generating one of the control signals to turn off the MOSFET transistor and generating the other of the control signals to turn on the other MOSFET transistor as a function of the supply voltage magnitude to make the slew rate of the resulting transition substantially insensitive to variations in power supply voltage.

Abstract: Some embodiments of the invention include a delay locked loop having a delay line for delaying an input signal. The input signal is generated from a first signal. A delay controller controls the delay line to adjust the timing relationship between the first signal and an internal signal. The delay locked loop also includes cycle control circuitry for controlling the cycle time of the signal entering the delay line and the cycle time of the signal exiting the delay line.

Abstract: Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows various timing specifications to be met when they would otherwise be violated, therefore improving data integrity in the system.

Abstract: A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components.

Abstract: Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus preventing premature or delayed enablement of utilization circuitry (e.g., memory). In addition, the trip-point remains constant during both slow and fast power up and power down conditions. This may be accomplished with the use of bandgap reference circuitry that provides a stable bandgap reference voltage when operating in its stable operating region. The bandgap circuitry operates in conjunction with startup circuitry, which enables the bandgap circuitry to operate in its non-stable operating region. When in the non-stable region, the bandgap circuitry provides a source voltage as the reference voltage until the source voltage begins to approach the bandgap voltage, at which point the bandgap circuitry provides the stable bandgap reference voltage as the reference voltage.

Abstract: A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components.

Abstract: A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals synchronized. The delay locked loop also includes cycle control circuitry for controlling the cycle time of the signal entering the delay and the cycle time of the signal exiting the delay line.

Abstract: An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to the supply voltages is affected by the magnitude of at least one of the supply voltages. The output buffer is driven by a pre-driver coupling first and second control signals to the first and second MOSFET transistors, respectively. The pre-driver adjusts the delay between generating one of the control signals to turn off the MOSFET transistor and generating the other of the control signals to turn on the other MOSFET transistor as a function of the supply voltage magnitude to make the slew rate of the resulting transition substantially insensitive to variations in power supply voltage.

Abstract: An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to the supply voltages is affected by the magnitude of at least one of the supply voltages. The output buffer is driven by a pre-driver coupling first and second control signals to the first and second MOSFET transistors, respectively. The pre-driver adjusts the delay between generating one of the control signals to turn off the MOSFET transistor and generating the other of the control signals to turn on the other MOSFET transistor as a function of the supply voltage magnitude to make the slew rate of the resulting transition substantially insensitive to variations in power supply voltage.

Abstract: Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows various timing specifications to be met when they would otherwise be violated, therefore improving data integrity in the system.

Abstract: Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus preventing premature or delayed enablement of utilization circuitry (e.g., memory). In addition, the trip-point remains constant during both slow and fast power up and power down conditions. This may be accomplished with the use of bandgap reference circuitry that provides a stable bandgap reference voltage when operating in its stable operating region. The bandgap circuitry operates in conjunction with startup circuitry, which enables the bandgap circuitry to operate in its non-stable operating region. When in the non-stable region, the bandgap circuitry provides a source voltage as the reference voltage until the source voltage begins to approach the bandgap voltage, at which point the bandgap circuitry provides the stable bandgap reference voltage as the reference voltage.

Abstract: A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components.

Abstract: Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows various timing specifications to be met when they would otherwise be violated, therefore improving data integrity in the system.

Abstract: Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus preventing premature or delayed enablement of utilization circuitry (e.g., memory). In addition, the trip-point remains constant during both slow and fast power up and power down conditions. This may be accomplished with the use of bandgap reference circuitry that provides a stable bandgap reference voltage when operating in its stable operating region. The bandgap circuitry operates in conjunction with startup circuitry, which enables the bandgap circuitry to operate in its non-stable operating region. When in the non-stable region, the bandgap circuitry provides a source voltage as the reference voltage until the source voltage begins to approach the bandgap voltage, at which point the bandgap circuitry provides the stable bandgap reference voltage as the reference voltage.

Abstract: A delay locked loop includes a forward path for receiving an input signal to provide an output signal, a feedback path for providing a feedback signal based on the output signal, and a controller responsive to a timing relationship between the feedback signal and the input signal for adjusting a timing of the output signal. The feedback path includes an adjustable delay circuit for adjusting a timing of the feedback signal.

Abstract: Some embodiments of the invention include a delay locked loop having a delay line for delaying an input signal. The input signal is generated from a first signal. A delay controller controls the delay line to adjusting the timing relationship between the first signal and the internal signal. The delay locked loop also includes cycle control circuitry for controlling the cycle time of the signal entering the delay line and the cycle time of the signal exiting the delay line. Other embodiments are described and claimed.

Abstract: An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to the supply voltages is affected by the magnitude of at least one of the supply voltages. The output buffer is driven by a pre-driver coupling first and second control signals to the first and second MOSFET transistors, respectively. The pre-driver adjusts the delay between generating one of the control signals to turn off the MOSFET transistor and generating the other of the control signals to turn on the other MOSFET transistor as a function of the supply voltage magnitude to make the slew rate of the resulting transition substantially insensitive to variations in power supply voltage.

Abstract: The illustrated embodiments relate to a control circuit that is adapted to use a latency signal to generate an output signal. The latency is adapted to be used to create a control signal that is dependent on the latency signal. The control signal is adapted to be used to select from among multiple input sources. The selected input source is adapted to be used to create an output signal.

Abstract: Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus preventing premature or delayed enablement of utilization circuitry (e.g., memory). In addition, the trip-point remains constant during both slow and fast power up and power down conditions. This may be accomplished with the use of bandgap reference circuitry that provides a stable bandgap reference voltage when operating in its stable operating region. The bandgap circuitry operates in conjunction with startup circuitry, which enables the bandgap circuitry to operate in its non-stable operating region. When in the non-stable region, the bandgap circuitry provides a source voltage as the reference voltage until the source voltage begins to approach the bandgap voltage, at which point the bandgap circuitry provides the stable bandgap reference voltage as the reference voltage.