Abstract: The invention relates to a method and a device for reading/writing data elements from/into a shared FIFO buffer, wherein the signalling that a data element or a storage space for a data element is available in a FIFO buffer, i.e. performing a V-operation, is not performed atomically as soon as a data element or a storage space for a data element becomes available in said FIFO buffer but to wait until L data elements or L storage spaces for L data elements have become available in said FIFO buffer before performing one signalling of the availability of the L data elements or L storage spaces for L data elements. In a sense, the signalling of the availability of the data elements or the storage spaces for data elements, i.e. performing a V-operation, is buffered until a certain amount of V-operations is collected before outputting of the signalling of the availability.

Abstract: A V-operation not performed atomically for each data element or storage space that becomes available in a FIFO or a P-operation is not performed atomically for each request for a data element or a storage space in the FIFO but rather one V-operation is performed after m data elements or m storage spaces have become available in the FIFO or one P-operation is performed after m requests for data elements or m requests for storage spaces have been received. Upon using these P-operations, i.e. performing said request operations in bursts rather than atomically, cases may occur where less data elements or storage spaces are available in said FIFO buffer than needed or requested by a consumer process, e.g. a reading or a writing process. A P-operation is performed by requesting m data elements or m storage spaces for m data elements. The P-operation will only be blocked completely, if no data elements or storage spaces are available in the FIFO buffer, i.e. the semaphore counter being zero.

Abstract: A processor cluster according to the invention is implemented on a single integrated circuit comprising a configurable cache memory (1) and a plurality of processors (2a, . . . , 2e). At least two processors (2a, 2b) have mutually different instruction sets. The processor cluster further comprises a selection unit (6) for selectively activating one of the plurality of processors and giving said selected processor access to the cache memory.

Abstract: A data processing apparatus has a main memory that contains memory locations with mutually different access latencies. Information from the main memory is cached in a cache memory. When cache replacement is needed selection of a cache replacement location depends on differences in the access latencies of the main memory locations for which replaceable cache locations are in use. When an access latency of a main memory location cached in the replaceable cache memory location is relatively smaller than an access latency of other main memory locations cached in other replaceable cache memory locations, the cached data for that main memory location is replaced by preference over data for the other main memory locations, because of its smaller latency.

Abstract: A way prediction scheme for a partitioned cache is based on the contents of instructions that use indirect addressing to access data items in memory. The contents of indirect-address instructions are directly available for use, without a memory address computation, and a prediction scheme based on this directly available information is particularly well suited for a pipeline architecture. Indirect addressing instructions also provide a higher-level abstraction of memory accesses, and are likely to be more indicative of relationships among data items, as compared to the absolute address of the data items. In a preferred embodiment, the base register that is contained in the indirect address instruction provides an index to a way-prediction table for an n-way associative cache.

Abstract: A way prediction scheme for a partitioned cache is based on the contents of instructions that use indirect addressing to access data items in memory. The contents of indirect-address instructions are directly available for use, without a memory address computation, and a prediction scheme based on this directly available information is particularly well suited for a pipeline architecture. Indirect addressing instructions also provide a higher-level abstraction of memory accesses, and are likely to be more indicative of relationships among data items, as compared to the absolute address of the data items. In a preferred embodiment, the base register that is contained in the indirect address instruction provides an index to a way-prediction table for an n-way associative cache.

Abstract: A data processing apparatus has a main memory that contains memory locations with mutually different access latencies. Information from the main memory is cached in a cache memory. When cache replacement is needed selection of a cache replacement location depends on differences in the access latencies of the main memory locations for which replaceable cache locations are in use. When an access latency of a main memory location cached in the replaceable cache memory location is relatively smaller than an access latency of other main memory locations cached in other replaceable cache memory locations, the cached data for that main memory location is replaced by preference over data for the other main memory locations, because of its smaller latency.

Abstract: A source program is executed on microcontroller core 114 of a processing unit 100. The core 114 is capable of native instructions from a predetermined set of micro-controller specific instructions. In a pre-processing step, for the program statements of the source program a program-specific virtual machine is defined with a corresponding set of virtual machine instructions, such that the expression of the program statements in the sequence of instructions requires less storage space compared to using only native instructions. For the program-specific virtual machine an associated conversion means 132 is defined for converting the program-specific virtual machine instructions into the native instructions of the core 114. The source program statements are expressed in a sequence of instructions comprising instructions of the defined virtual machine. The sequence of instructions is stored in an instruction memory 120. The conversion means 114 is represented in the processing unit 100.