Abstract: A method and apparatus for protecting the stored information on an integrated circuit from being compromised through reverse engineering. To do so, the method and apparatus splits the functionality of an integrated circuit into two separate integrated circuits, which are then connected in an interlocking manner. A detection circuit monitors the interconnection of the two separate integrated circuits. Upon detection of a break in the interconnection of the two circuits, the detection circuit destroys the data stored in the two separate integrated circuits. The two integrated circuits are connected in a flip-chip fashion, thereby preventing access to the underlying conduction paths and charge storage sites which are normally used in reverse engineering an integrated circuit.

Abstract: The specification describes techniques for soldering IC chips, or other components, to interconnection substrates using a patterned epoxy layer to define the solder interconnections. The epoxy layer is photodefined to form openings that expose the bonding sites on the IC chip (or alternatively the interconnect substrate). Solder paste is deposited in the openings. With the IC chip and the interconnect substrate aligned together, the solder paste is heated to reflow the solder and solder bond the IC chip to the substrate. Heating is continued to cure the epoxy, which serves the function of the conventional underfill. The shape of the solder interconnection is defined by the lithographically formed openings, and the interconnections can be made with very fine pitch. The application of the epoxy underfill in this manner assures complete filling of the gap between the IC chip and the interconnection substrate.

Abstract: A thin film capacitor for use in semiconductor integrated circuit devices such as analog circuits, rf circuits, and dynamic random access memories (DRAMs), and a method for its fabrication, is disclosed. The capacitor has a dielectric thickness less than about 50 nm, a capacitance density of at least about 15 fF/.mu.m.sup.2, and a breakdown field of at least about 1 MV/cm. The dielectric material is a metal oxide of either titanium, niobium, or tantalum. The metal oxide can also contain silicon or nitrogen. The dielectric material is formed over a first electrode by depositing the metal onto the substrate or onto a first electrode formed on the substrate. The metal is then anodically oxidized to form the dielectric material of the desired thickness. A top electrode is then formed over the dielectric layer. The top electrode is a metal that does not degrade the electrical characteristics (e.g. the leakage current or the breakdown voltage) of the dielectric layer.

Abstract: A battery cell stick (100) is formed by vertically-stacking bare rechargeable cylindrical battery cells (110, 120) and then wrapping the cells in a common label (130) having an adhesive backing (132). Subsequently, multiple cell sticks (100, 150) are combined in a single plastic housing (160). The assembly is wrapped with an additional adhesive-backed label (180). Positively- and negatively-polarized terminal ends (112, 152) are exposed through openings (172, 174) in the housing.

Abstract: A dental floss device (1, 40, 50, 60, 70) comprises a handle (2) having a shank (3) terminating in a head piece (4). A disposable dental floss holder (5) comprises a base portion (10) and a pair of spaced-apart jaws (11, 12) with a length of dental floss (13) extending therebetween. The head piece (4) has a groove (20) in which the base portion (10) is securely retained when the device is used in all flossing directions. Snap-fit projections (15) extend inwardly from the jaws (11, 12) of the floss holder (5) and are retained behind marginal edges (25) of a floor (24) of the groove (20). When used, the floss holder (5) is removed and a new floss holder (5) is fitted.

Abstract: A fuse programmable ROM includes a wafer for a CMOS-type structure having an emitter, which emitter is overlain by a fuse pad of an undoped polysilicon and a conductive layer. There is a layer of barrier oxide disposed on the conductive top layer of the fuse pad and a sidewall oxide surrounding the periphery of the fuse pad both of which are overlain by the metallic electrical connection.The process of producing the fuse programmable ROM includes wide utilization of standard CMOS fabrication techniques with which are included the steps of depositing fuse material of undoped polysilicon, forming the fuse material into a fuse pad, and then making an electrical connection with the fuse pad.

Abstract: A process for using selectively deposited tungsten in the making of ohmic contacts and contact/interconnect metallization patterns. In one form the process is employed to interconnect fully formed field effect devices using contacts through the dielectric layer. A thin layer of intrinsic polysilicon or amorphous silicon is conformally deposited, patterned and covered by selectively deposited tungsten, An anneal operation then forms self-aligned contacts or shunts, between the tungsten layer and the source/drain type diffusions exposed during the contact cut, by updiffusion through the thin intrinsic silicon, or by conversion of the thin intrinsic silicon to tungsten.

Abstract: A process for fabricating a bipolar transistor with a thin base and an abrupt base-collector junction includes the steps of depositing a thin layer of polycrystalline or amorphous silicon base material in a single crystal collector region, while in-situ doping the deposited silicon with boron atoms, and thereafter, recrystallizing the deposited silicon layer by thermal-pulse annealing at a temperature high enough to effect recrystallization and solid phase epitaxial regrowth while low enough to minimize interdiffusion of dopants between the base and collector.The process further includes providing the transistor fabricated by the aforedescribed steps with an abrupt base-emitter junction. This is accomplished by depositing n.sup.++ doped polysilicon with a LPCVD process and thereafter thermal annealing the polysilicon.

Abstract: A process for forming high performance npn bipolar transistors in an enhanced CMOS process using only one additional mask level. The bipolar transistor is formed using a low dose blanket implant to form the base in the substrate n-well, then applying arsenic-implanted polysilicon to form the emitter. The emitter formation involves forming a blanket polysilicon layer over the wafer, then using the additional photomask to confine the subsequent arsenic implant to the emitter, n.sup.+ and polysilicon contact regions, prior to application of aluminum metallization. The arsenic implanted polysilicon technique provides state-of-the-art bipolar processing as well as improved contact characteristics. The combined polysilicon-aluminum metallization improves step coverage, circuit reliability, and reduces the possibility of aluminum diffusion (spiking) through junctions.

Abstract: The specification describes a process for minimizing ion scattering and thereby improving resolution in ion beam lithography. First, a substrate coated with a layer of ion beam resist is provided at a chosen spaced distance from an ion beam source. Next, a monocrystalline membrane with a patterned ion absorption region is positioned at a predetermined location between the substrate target and the ion beam source. The patterned ion absorption region may be either an ion absorption mask, such as gold, deposited on the surface of the monocrystalline membrane, or a pattern of ion-damaged regions within the monocrystalline membrane. Finally, a collimated wide area ion beam is passed perpendicular to the surface of the membrane and through crystal lattice channels therein which are exposed by the patterned ion absorption region and which extend perpendicular to the membrane surface.

Abstract: The specification describes a process and apparatus for aligning a mask and semiconductor wafer during X-ray lithography which comprises, among other things, inserting a novel flexible spacer between the mask and wafer so as to maintain a vacuum seal between the mask and wafer. This spacer has a plurality of selectively spaced studs with flat surfaces adapted to receive the mask and wafer in intimate contact and conform to surface variations thereon. This spacer serves to maintain a substantially constant distance between mask and wafer over the entire facing surfaces of these two members during an X-ray lithographic process. A sealing member is disposed at the periphery of the flexible spacer and is also in intimate contact with the mask and wafer so as to maintain a vacuum seal between the mask and wafer. The facing surfaces of the mask and wafer will be forced against the studs on the spacer by atmospheric pressure so long as a vacuum is maintained in the sealed space between the mask and wafer.

Abstract: The specification describes a process wherein short wavelength or "hard" x-rays (less than about 4 Angstroms) are used to align a semiconductor processing mask with a semiconductor wafer without the requirement for thinning the wafer to permit the x-rays to pass through. These short wavelength x-rays may be obtained from either the continuum x-rays which accompany the "soft" (longer wavelength) characteristic x-rays used for resist exposure, or from a specialized source of hard x-rays. Alternatively, alignment marks may be provided on the surface of the wafer to project alignment-indicative fluorescent x-rays onto an x-ray detector without passing through the underlying semiconductor wafer. A null condition in the intensity of the "hard" x-rays, or the fluorescent x-rays in the alternative embodiment of the invention, which are received at an x-ray detector is indicative of an alignment between a reference mark on the mask and either a reference mark or an opening on the wafer.

Abstract: Alignment of a mask and a semiconductor wafer to be processed is effected by orthogonal and angular movements of the mask singly and in combination. A carrier for the mask is supported on four orthogonally positioned transducers which, when actuated to elongate or contract, produce carrier translational movement in either or both orthogonal directions and/or rotational movement by selective elongation and contraction of one or more transducers. Actuation of the transducers and the alignment are obtained by signals from a feedback system including photon detection and multiple frequency oscillation utilizing alignment marks on the mask and the wafer.