Abstract: A quad leadframe (22') for a CERQUAD is manufactured using conventional cladding and stamping technologies. A first metal layer (12) is provided with multiple cavities (14). A second metal layer (14) is clad to the first metal layer. A leadframe strip (22) can then be stamped from the clad metal. The leadframe has a leads (24) and bonding posts (28). The leads comprise two metal layers, and the bonding posts comprise only the second metal layer. The leadframe can then be used in the assembly of a semiconductor device (32). The portion of the leads external to the package body can be optionally etched to remove the second metal layer.

Abstract: Contaminants are removed from a semiconductor material by heating the semiconductor material to temperature within the range of a minimum temperature where a halogen compound will decompose to halogen atoms without the use of ultraviolet irradiation and react with contaminants present on the semiconductor material and a maximum temperature of 800.degree. C., wherein less than or equal to approximately 50 Angstroms of oxide is formed on the semiconductor material. The ambient in which the semiconductor material is heated is an ambient comprised of a nonreactive gas and a halogen compound for at least a time sufficient to remove a substantial amount of contaminants from the semiconductor material.

Abstract: A semiconductor multiple package module (10) on a PCB material substrate (18) is provided, wherein semiconductor dice are directly mounted onto the PCB material substrate (18) thereby eliminating a subsequent board mounting at the customer level. A plurality of semiconductor dice are mounted and electrically connected to a plurality of circuit traces (22) on the PCB material substrate (18) having a plurality of edge connectors (20). The plurality of circuit traces (22) has conductive paths to electrically interconnect the semiconductor dice to the edge connectors (20) and to each other. The semiconductor dice are directly overmolded on the PCB material substrate (18) with a molding compound to form individual semiconductor devices (12, 14, and 16) having separate package bodies. The individualized package bodies enable repair to the module by making removal of only nonfunctional semiconductor devices from the PCB material substrate (18) possible.

Abstract: A low cost manufacturing method is used to fabricate a small multichip semiconductor device (30). In one embodiment, a pattern of conductive traces (13) is formed on a film of transfer material (12). A first semiconductor die (15) is interconnected to the traces and a resin body (20) is formed around the first die and one side of the traces. The film of transfer material forms, at this stage of the process, one side of the first package. The film of transfer material is then peeled from the pattern of conductive traces and the first resin body to expose the other side of the traces. A second semiconductor die (23) is interconnected to the exposed side of the traces. A second resin body (25) is formed around the second die and portions of the exposed traces. Solder balls (26) are coupled to the exposed portions of the traces to establish external electrical connections to each die.

Abstract: A composite flip chip semiconductor device (10) permits burn-in testing and rework to be performed on the device while also enhancing electrical, thermal, and mechanical device performance. The device includes a semiconductor die (12) having a plurality of bonding pads (14). Also included in the composite device is an interposer (22) having a first surface with a plurality of traces (26). A plurality of vias (24) extend from the first surface of the interposer (22) to a second surface. The semiconductor die (12) is electrically coupled to the plurality of vias of the interposer which in turn is to be coupled to a substrate.

Abstract: A stackable three dimensional leadless multi-chip module (10) is provided whereby each level of semiconductor device (11) is interconnected to another level through reflowing of solder plated wires (22). Each semiconductor device (11) contains a semiconductor die (24) overmolded by a package body (12) on a PCB substrate (14) having a plurality of edge metal conductors (16) that form half-vias (18). The half-vias (18) at the edges of substrate (14) give the substrate a castellated appearance, where the castellations serve as the self-aligning feature during the stacking of the devices (11). Each device (11) is simply stacked on top of each other without any additional layers to give the semiconductor module (10) a lowest possible profile. A plurality of solder plated wires (22) fits into the half-vias (18) and is solder reflowed to the metal conductors (16) to interconnect the semiconductor devices (11). The wires (22) are bent to enable the module (10) to be surface mounted to a PC board.

Abstract: A low cost manufacturing method is used to fabricate a small multiple chip semiconductor device (10). In one embodiment, a first pattern of conductive traces (14) is formed on one surface of a substrate (12), and a second pattern of traces (16) is formed on a second surface of the substrate (12). A first semiconductor die (20) is interconnected to the first traces (14), and a package body (24) is formed around the first die and a portion of the traces. A second semiconductor die (26) is interconnected to the second traces (16) on the second surface. A second package body (28) is formed around the second die and a portion of the traces (16). Solder balls (32) are coupled to exposed portions of the second traces (16) around the perimeter of the package body (28) to establish external power and ground connections to each die. Edge leads (36) are externally soldered to the traces (14 & 16) around the periphery of the substrate (12) to establish remaining electrical connections.

Abstract: A stackable three-dimensional multi-chip module (MCM) is provided whereby each level of chip carrier is interconnected to another level of chip carrier through reflowing of solder balls pre-bumped onto each carrier. Each level of chip carrier, except for the top carrier, has solder balls on both top and bottom surfaces of the substrate. Optional lids can be used to seal each device, and the lid height would serve as a natural positive stand-off between each level of carriers, giving rise to hour glass shaped solder joints which maximizes the fatigue life of the joints. Heat sinks to further enhance heat dissipation of the MCM can be easily accommodated in this stacking approach. Furthermore, each substrate is capable of carrying multiple chips, so the module incorporates planar chip density growth concurrently with the three-dimensional growth giving rise to an ultradense MCM.

Abstract: Solder balls are transferred onto a semiconductor device (50), for example a flip chip semiconductor device, without using solder evaporation techniques. In one form, pre-formed solder balls (36) are placed in recesses (32) formed in a transfer substrate (30). A semiconductor die (12) having a plurality of bond pads (14) is positioned with respect to the transfer substrate so that the solder balls are aligned to, and in contact with, the bond pads. The solder balls are then reflowed to form a metallurgical bond to the bond pads. One embodiment of the invention utilizes a transfer substrate made of silicon so that the coefficient of thermal expansion of the transfer substrate will closely match that of the semiconductor die, thereby minimizing solder ball alignment variances. Use of silicon as a transfer substrate material also allows the recesses to easily be made non-wettable by conventional silicon oxidation techniques.

Abstract: A semiconductor device is disclosed having an electronic component mounted to a mounting surface opposite a heat transfer surface of a die support member. The electronic component includes a plurality of bonding pads each electrically coupled to a plurality of package leads by a number of inner leads. A package body encloses the electronic component, the inner leads, the proximal ends of the package leads and the mounting surface of the die support member. The package body includes an opening exposing a portion of the heat transfer surface of the die support member. An insertable thermally conductive heat sink extends into the opening in the package body making thermal contact with the heat transfer surface of the die support member. A thermally conductive electrically insulating adhesive joins the heat sink to the package body securing the heat sink to the package body. In the assembly process, the package body is formed prior to attachment of the heat sink.

Abstract: A semiconductor device (10) having first and second wiring layers (30, 33) on opposite surfaces of a carrier substrate (12) interconnected through vias (32) formed in the carrier substrate (12) electrically coupling an electronic component (18) to a mounting substrate through compliant solder balls (26) displaced away from vias (32), the semiconductor device (10) characterized by a standard size carrier substrate (12) having high performance electrical package interconnections (24) and good heat dissipation. Improved electrical performance is obtained by providing independent wiring layers (30, 33) each having a lead trace layout specifically designed for a particular electronic component (18) and a particular board connection requirement while using a standard size package outline. Assembly costs are reduced by providing a plastic package mold (36) over a standard size carrier substrate (12) capable of supporting a variety of different electronic components (18) themselves having varying dimensions.

Abstract: A semiconductor device and a method for its fabrication are disclosed. In a preferred embodiment, a pattern of conductive traces is formed on a film of transfer material. A semiconductor device die is interconnected to the pattern of conductive traces and a resin body is formed around the die, one side of the conductive traces, and the interconnecting means. The film of transfer material forms, at this stage of the process, one side of the package. The film of transfer material is then peeled from the pattern of conductive traces and the resin body to expose the other side of the pattern of conductive traces. Contact to the other side of the pattern provides electrical contact to the senmiconductor device die.

Abstract: A semiconductor device having both bottom-side contacts and peripheral contacts provides surface mounting options. In one form, a semiconductor device die is positioned at a die receiving area of a leadframe. The leadframe also has a plurality of leads, each lead having a first and a second contact portion which are separated by an intermediate portion. A package body encapsulates the semiconductor device die and intermediate portions of the plurality of leads. The first contact portions of the leads are partially exposed on the bottom surface of the package body. The second contact portions extend from the package body along a portion of the package body perimeter. The first contact portions provide bottom-side contacts to the device, while the second contact portions provide peripheral contacts. The second contact portions are shaped into a desired lead configuration or are severed to establish a leadless device.

Abstract: The disclosed invention comprises multiple semiconductor devices within a single carrier structure. In accordance with one embodiment of the invention, a plurality of semiconductor die are coupled to the leads of a leadframe and are encapsulated by individual package bodies. A carrier structure is formed which encircles all of the die and encapsulates portions of the distal ends of the leads. The extreme distal portions of the leads extend through the carrier to form contact points which are used to access the semiconductor die. By having multiple devices within a single carrier, productivity is improved and costs associated with leadframe and carrier structure materials are reduced.

Abstract: An electronic component having a flexible substrate with conductive traces thereon may have the leads separated into arrays that are shaped to contact and be surface mounted to the bonding lands on a printed circuit board (PCB). The flexible substrate, such as polyimide, adheres to the traces and is formed into lead arrays with them. The lead arrays thus keep portions of the leads and the outer bonding areas corresponding thereto aligned with respect to each other during handling and mounting to the PCB. An alignment mechanism may be optionally present on the lead arrays that mates with a corresponding mechanism on the PCB. The package body itself may be overmolded, assembled from prior parts, etc. Another alternative version includes test points on the perimeter of the substrate beyond the outer bonding areas that may be used to test the device, such as an integrated circuit chip or die, at an intermediate stage in the assembly process.

Abstract: A method for fabricating and especially for encapsulating a semiconductor device in a plastic package is disclosed. In accordance with one embodiment of the invention the method includes steps of providing an encapsulation mold having a first chamber and a second chamber, with the second chamber spaced outwardly from and substantially surrounding the first chamber. The first chamber is shaped to receive a removable insert. An insert is selected for the particular body type and style which is desired and that insert is secured in the first chamber. The insert has a cavity which is shaped to define the desired encapsulated device package body. A lead frame is provided including a bonding area and a plurality of leads, each lead having a inner portion near the bonding area and an outer portion extending outwardly from the bonding area.

Abstract: A pad array electronic device for mounting on a substrate, such as a printed circuit board (PCB), has a relatively rigid package body with a plurality of holes bearing connecting mechanisms for bonding to lands on the PCB. The package body may be a thermoset plastic or other material that can be injection molded around an electronic component, such as an integrated circuit (IC) bonded to a lead frame. An integrated circuit die or other electronic component is mounted in proximity with or on the lead frame and electrical connections between the integrated circuit chip and the frame are made by any conventional means. In one aspect, the substrate leads are provided at their outer ends that are exposed by holes in the package with solder balls or pads for making connections to the PCB. The package body may be optionally used to stand off the device a set distance from the PCB so that the solder balls will form the proper concave structure.

Abstract: An electronic pad array carrier IC device for mounting on a printed circuit board (PCB) or flex circuit substrate has a thin, flexible "tape" substrate having a plurality of traces. The substrate may be a polyimide or other material that can withstand relatively large lateral mechanical displacement. An integrated circuit die is mounted in proximity with or on the substrate and electrical connections between the integrated circuit chip and the traces are made by any conventional means. The substrate traces are provided at their outer ends with solder balls or pads for making connections to the PCB. A package body covers the die, which body may be optionally used to stand off the package a set distance from the PCB so that the solder balls will form the proper concave structure. Alternatively, a carrier structure may be provided around the periphery of the substrate to add rigidity during handling, testing and mounting, but which may also provide the stand-off function.

Abstract: The disclosed invention comprises multiple semiconductor devices within a single carrier structure. In accordance with one embodiment of the invention, a plurality of semiconductor die are coupled to the leads of a leadframe and are encapsulated by individual package bodies. A carrier structure is formed which encircles all of the die and encapsulates portions of the distal ends of the leads. The extreme distal portions of the leads extend through the carrier to form contact points which are used to access the semiconductor die. By having multiple devices within a single carrier, productivity is improved and costs associated with leadframe and carrier structure materials are reduced.

Abstract: An electronic component having a flexible substrate with conductive traces thereon may have the leads separated into arrays that are shaped to contact and be surface mounted to the bonding lands on a printed circuit board (PCB). The flexible substrate, such as polyimide, adheres to the traces and is formed into lead arrays with them. The lead arrays thus keep portions of the leads and the outer bonding areas corresponding thereto aligned with respect to each other during handling and mounting to the PCB. An alignment mechanism may be optionally present on the lead arrays that mates with a corresponding mechanism on the PCB. The package body itself may be overmolded, assembled from prior parts, etc. Another alternate version includes test points on the perimeter of the substrate beyond the outer bonding areas that may be used to test the device, such as an integrated circuit chip or die, at an intermediate stage in the assembly process.