Abstract: An improved packaged semiconductor device is provided having an electronic component, such as an integrated circuit, enclosed within a single layer ceramic PGA package. A cap, of substantially the same areal dimension as the base, is sealed to the base forming a cavity in which the integrated circuit is mounted. Input/output pins are attached to through-holes in the base and extend through the base and are exposed by holes in the cap aligned to the through-holes in the base. Extensive glass sealing of the cap to the base, made possible by the substantially co-extensive nature of the cap with respect to the base, provides a sturdy highly reliable seal making the packaged semiconductor device better able to withstand mechanical stress.

Abstract: An electronic device package on a lead frame with a peripheral carrier structure holding the distal ends of the leads in rigid position. The carrier structure is spaced apart from the package body and permits the package to be handled and tested while protecting the leads. A different, relatively lower quality and less expensive material is used for the carrier structure than for the package body to reduce the cost of the package since the carrier structure may comprise several times, for example four times or more, the volume of the package body.

Abstract: An electronic device package on a lead frame with a peripheral carrier structure holding the distal ends of the leads in rigid position. The carrier structure is spaced apart from the package body and permits the package to be handled and tested while protecting the leads. A different, relatively lower quality and less expensive material is used for the carrier structure than for the package body to reduce the cost of the package since the carrier structure may comprise several times, for example four times or more, the volume of the package body.

Abstract: A process for making hermetic, low cost pin grid array (PGA) semiconductor die packages. The process involves die bonding a semiconductor die or integrated circuit chip to a substrate having an interconnect or metallization pattern thereon. The die is electrically connected to the pattern and then the die and the inner bonds are hermetically sealed inside a cap that is smaller than the substrate so that the ends of the metallization pattern are exposed. The leads are then electrically connected, such as by solder or other technique to the exposed ends of the pattern.

Abstract: A mounting means for a semiconductor integrated circuit, the mounting means comprising a semiconductor material having a mounting surface as one major surface thereof, a semiconductor integrated circuit mounted on the major surface of the semiconductor material, and means for electrically connecting the integrated circuit to the semiconductor material. The mounting means has a coefficient of thermal expansion similar to the semiconductor integrated circuit mounted thereon.

Abstract: An integrated circuit package having a plurality of leads capable of holding a quantity of solder paste prior to bonding to a printed circuit board or other substrate. The solder paste bearing structure may be straight or spiral grooves, or even a slot or roughened surface, running down at least the lower length of the leads as long as some mechanism is present which will first hold the solder paste or other electrically conductive binder on the lead and then deliver the binder to the end of the lead to produce an electrical and structural bond in a binder flowing operation. Application of the solder paste to the leads is accomplished by simply dipping the package leads into the paste thereby eliminating the need to make a solder mask for the substrate as well as the task of aligning the mask to the substrate.

Abstract: A process is disclosed for fabricating a MOS ROM which allows programming of the ROM late in the process sequence. A conventional silicon gate process is used to fabricate the devices up through the step of patterning the polycrystalline silicon gate electrode. Selected devices in the array are then programmed to an off-state by fabricatng those devices with either the source or drain region offset from the gate electrode. This is accomplished by a programming mask which, together with the gate electrode, provides selective location of the source or drain regions. Devices having an offset source or drain are off-state devices, while those having a normal source and drain function conventionally and conduct when a read voltage is applied.

Abstract: A multilayer ceramic, multi-chip, dual in-line packaging assembly comprises a ceramic substrate with a pair of semiconductor chip receiving cavities therein. A metalization pattern partially embedded within the substrate provides electrical paths for semiconductor chip devices joined thereto to external circuitry. Semiconductor chips are joined to exposed pads within the chip receiving cavities. Metalization spaced from and positioned beneath the semiconductor chip devices completes interconnections between semiconductor chip devices. Exposed finger areas are spaced from one another and about the semiconductor chip receiving cavities. Embedded lines extend from the finger areas to external circuitry and interconnection means extend between finger areas.