Patents by Inventor Paul Tervo

Paul Tervo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7068057
    Abstract: A low-current pogo probe card for measuring currents down to the femtoamp region includes a laminate board having a layer of conductive traces interposed between two dielectric layers. A plurality of probing devices, such as ceramic blades, are edge-mounted about a central opening so that the probing needles or needles included therein terminate below the opening in a pattern suitable for probing a test subject workpiece. A plurality of pogo pin receiving pad sets, each including a guard pad, occupy the periphery of the board. Each guard pad is electrically connected to a trace from the layer of conductive traces. The pad sets may be connected to the probing devices by low noise cables or traces. Air trenches separate the pad sets for reducing cross talk and signal settling times.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: June 27, 2006
    Assignee: Cascade Microtech, Inc.
    Inventors: Paul A. Tervo, Clarence E. Cowan
  • Publication number: 20060132157
    Abstract: A wafer probe station is equipped with an integrated environment control enclosure substantially surrounding a supporting surface for holding a test device, such enclosure limiting fluid communication between the interior and exterior of the enclosure and preferably also providing EMI shielding and a dark environment. The limited communication between the interior and exterior of the enclosure is kept substantially constant despite positioning movement of either the supporting surface or probes. The positioning mechanisms for the supporting surface and probes each are located at least partially outside of the enclosure.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 22, 2006
    Inventors: Warren Harwood, Paul Tervo, Martin Koxxy
  • Patent number: 7042241
    Abstract: A probe card includes a plurality of probes, where each probe is supported by the probe card. A plurality of landings are on the top of the probe card. Each of the landings is electrically interconnected with a coaxial cable that is also associated with one of the probes. A plurality of trenches defined by the probe card substantially encircles respective landings.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: May 9, 2006
    Assignee: Cascade Microtech, Inc.
    Inventors: Paul A. Tervo, Clarence E. Cowan
  • Patent number: 7009383
    Abstract: A wafer probe station is equipped with an integrated environment control enclosure substantially surrounding a supporting surface for holding a test device, such enclosure limiting fluid communication between the interior and exterior of the enclosure and preferably also providing EMI shielding and a dark environment. The limited communication between the interior and exterior of the enclosure is kept substantially constant despite positioning movement of either the supporting surface or probes. The positioning mechanisms for the supporting surface and probes each are located at least partially outside of the enclosure.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: March 7, 2006
    Assignee: Cascade Microtech, Inc.
    Inventors: Warren K. Harwood, Paul A. Tervo, Martin J. Koxxy
  • Patent number: 6980012
    Abstract: A probe station includes a fully guarded chuck assembly and connector mechanism for increasing sensitivity to low-level currents while reducing settling times. The chuck assembly includes a wafer-supporting first chuck element surrounded by a second chuck element having a lower component, skirting component and upper component each with a surface portion extending opposite the first element for guarding thereof. The connector mechanism is so connected to the second chuck element as to enable, during low-level current measurements, the potential on each component to follow that on the first chuck element as measured relative to an outer shielding enclosure surrounding each element. Leakage current from the first chuck element is thus reduced to virtually zero, hence enabling increased current sensitivity, and the reduced capacitance thus provided by the second chuck element decreases charging periods, hence reducing settling times.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: December 27, 2005
    Assignee: Cascase Microtech, Inc.
    Inventors: Randy J. Schwindt, Warren K. Harwood, Paul A. Tervo, Kenneth R. Smith, Richard H. Warner
  • Publication number: 20050248359
    Abstract: A membrane probing assembly includes a probe card with conductors supported thereon, wherein the conductors include at least a signal conductor located between a pair of spaced apart guard conductors. A membrane assembly includes a membrane with contacts thereon, and supporting at least a signal conductor located between a pair of spaced apart guard conductors. The guard conductors of the probe card are electrically interconnected proximate the interconnection between the probe card and the membrane assembly. The guard conductors of the membrane assembly are electrically interconnected proximate the interconnection between the probe card and the membrane assembly.
    Type: Application
    Filed: June 3, 2005
    Publication date: November 10, 2005
    Inventors: Paul Tervo, Kenneth Smith, Clarence Cowan, Mike Dauphinais, Martin Koxxy
  • Publication number: 20050194983
    Abstract: A probe station includes a fully guarded chuck assembly and connector mechanism for increasing sensitivity to low-level currents while reducing settling times. The chuck assembly includes a wafer-supporting first chuck element surrounded by a second chuck element having a lower component, skirting component and upper component each with a surface portion extending opposite the first element for guarding thereof. The connector mechanism is so connected to the second chuck element as to enable, during low-level current measurements, the potential on each component to follow that on the first chuck element as measured relative to an outer shielding enclosure surrounding each element. Leakage current from the first chuck element is thus reduced to virtually zero, hence enabling increased current sensitivity, and the reduced capacitance thus provided by the second chuck element decreases charging periods, hence reducing settling times.
    Type: Application
    Filed: April 21, 2005
    Publication date: September 8, 2005
    Inventors: Randy Schwindt, Warren Harwood, Paul Tervo, Kenneth Smith, Richard Warner
  • Publication number: 20050184744
    Abstract: A probe station includes a fully guarded chuck assembly and connector mechanism for increasing sensitivity to low-level currents while reducing settling times. The chuck assembly includes a wafer-supporting first chuck element surrounded by a second chuck element having a lower component, skirting component and upper component each with a surface portion extending opposite the first element for guarding thereof. The connector mechanism is so connected to the second chuck element as to enable, during low-level current measurements, the potential on each component to follow that on the first chuck element as measured relative to an outer shielding enclosure surrounding each element. Leakage current from the first chuck element is thus reduced to virtually zero, hence enabling increased current sensitivity, and the reduced capacitance thus provided by the second chuck element decreases charging periods, hence reducing settling times.
    Type: Application
    Filed: February 11, 2005
    Publication date: August 25, 2005
    Inventors: Randy Schwindt, Warren Harwood, Paul Tervo, Kenneth Smith, Richard Warner
  • Patent number: 6930498
    Abstract: A membrane probing assembly includes a probe card with conductors supported thereon, wherein the conductors include at least a signal conductor located between a pair of spaced apart guard conductors. A membrane assembly includes a membrane with contacts thereon, and supporting at least a signal conductor located between a pair of spaced apart guard conductors. The guard conductors of the probe card are electrically interconnected proximate the interconnection between the probe card and the membrane assembly. The guard conductors of the membrane assembly are electrically interconnected proximate the interconnection between the probe card and the membrane assembly.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: August 16, 2005
    Assignee: Cascade Microtech, Inc.
    Inventors: Paul A. Tervo, Kenneth R. Smith, Clarence E. Cowan, Mike P. Dauphinais, Martin J. Koxxy
  • Publication number: 20050151557
    Abstract: A low-current pogo probe card for measuring currents down to the femtoamp region includes a laminate board having a layer of conductive traces interposed between two dielectric layers. A plurality of probing devices, such as ceramic blades, are edge-mounted about a central opening so that the probing needles or needles included therein terminate below the opening in a pattern suitable for probing a test subject workpiece. A plurality of pogo pin receiving pad sets, each including a guard pad, occupy the periphery of the board. Each guard pad is electrically connected to a trace from the layer of conductive traces. The pad sets may be connected to the probing devices by low noise cables or traces. Air trenches separate the pad sets for reducing cross talk and signal settling times.
    Type: Application
    Filed: February 7, 2005
    Publication date: July 14, 2005
    Inventors: Paul Tervo, Clarence Cowan
  • Publication number: 20050146345
    Abstract: A low-current pogo probe card for measuring currents down to the femtoamp region includes a laminate board having a layer of conductive traces interposed between two dielectric layers. A plurality of probing devices, such as ceramic blades, are edge-mounted about a central opening so that the probing needles or needles included therein terminate below the opening in a pattern suitable for probing a test subject workpiece. A plurality of pogo pin receiving pad sets, each including a guard pad, occupy the periphery of the board. Each guard pad is electrically connected to a trace from the layer of conductive traces. The pad sets may be connected to the probing devices by low noise cables or traces. Air trenches separate the pad sets for reducing cross talk and signal settling times.
    Type: Application
    Filed: January 5, 2005
    Publication date: July 7, 2005
    Inventors: Paul Tervo, Clarence Cowan
  • Publication number: 20050035779
    Abstract: A low-current pogo probe card for measuring currents down to the femtoamp region includes a laminate board having a layer of conductive traces interposed between two dielectric layers. A plurality of probing devices, such as ceramic blades, are edge-mounted about a central opening so that the probing needles or needles included therein terminate below the opening in a pattern suitable for probing a test subject workpiece. A plurality of pogo pin receiving pad sets, each including a guard pad, occupy the periphery of the board. Each guard pad is electrically connected to a trace from the layer of conductive traces. The pad sets may be connected to the probing devices by low noise cables or traces. Air trenches separate the pad sets for reducing cross talk and signal settling times.
    Type: Application
    Filed: September 22, 2004
    Publication date: February 17, 2005
    Inventors: Paul Tervo, Clarence Cowan
  • Patent number: 6856153
    Abstract: A low-current pogo probe card for measuring currents down to the femtoamp region includes a laminate board having a layer of conductive traces interposed between two dielectric layers. A plurality of probing devices, such as ceramic blades, are edge-mounted about a central opening so that the probing needles or needles included therein terminate below the opening in a pattern suitable for probing a test subject workpiece. A plurality of pogo pin receiving pad sets, each including a guard pad, occupy the periphery of the board. Each guard pad is electrically connected to a trace from the layer of conductive traces. The pad sets may be connected to the probing devices by low noise cables or traces. Air trenches separate the pad sets for reducing cross talk and signal settling times.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: February 15, 2005
    Assignee: Cascade Microtech, Inc.
    Inventors: Paul A. Tervo, Clarence E. Cowan
  • Publication number: 20050017741
    Abstract: A wafer probe station is equipped with an integrated environment control enclosure substantially surrounding a supporting surface for holding a test device, such enclosure limiting fluid communication between the interior and exterior of the enclosure and preferably also providing EMI shielding and a dark environment. The limited communication between the interior and exterior of the enclosure is kept substantially constant despite positioning movement of either the supporting surface or probes. The positioning mechanisms for the supporting surface and probes each are located at least partially outside of the enclosure.
    Type: Application
    Filed: August 25, 2004
    Publication date: January 27, 2005
    Inventors: Warren Harwood, Paul Tervo, Martin Koxxy
  • Publication number: 20050007131
    Abstract: A membrane probing assembly includes a probe card with conductors supported thereon, wherein the conductors include at least a signal conductor located between a pair of spaced apart guard conductors. A membrane assembly includes a membrane with contacts thereon, and supporting at least a signal conductor located between a pair of spaced apart guard conductors. The guard conductors of the probe card are electrically interconnected proximate the interconnection between the probe card and the membrane assembly. The guard conductors of the membrane assembly are electrically interconnected proximate the interconnection between the probe card and the membrane assembly.
    Type: Application
    Filed: July 29, 2004
    Publication date: January 13, 2005
    Inventors: Paul Tervo, Kenneth Smith, Clarence Cowan, Mike Dauphinais, Martin Koxxy
  • Patent number: 6838890
    Abstract: A membrane probing assembly includes a probe card with conductors supported thereon, wherein the conductors include at least a signal conductor located between a pair of spaced apart guard conductors. A membrane assembly includes a membrane with contacts thereon, and supporting at least a signal conductor located between a pair of spaced apart guard conductors. The guard conductors of the probe card are electrically interconnected proximate the interconnection between the probe card and the membrane assembly. The guard conductors of the membrane assembly are electrically interconnected proximate the interconnection between the probe card and the membrane assembly.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: January 4, 2005
    Assignee: Cascade Microtech, Inc.
    Inventors: Paul A. Tervo, Kenneth R. Smith, Clarence E. Cowan, Mike P. Dauphinais, Martin J. Koxxy
  • Patent number: 6822467
    Abstract: A low-current pogo probe card for measuring currents down to the femtoamp region includes a laminate board having a layer of conductive traces interposed between two dielectric layers. A plurality of probing devices, such as ceramic blades, are edge-mounted about a central opening so that the probing needles or needles included therein terminate below the opening in a pattern suitable for probing a test subject workpiece. A plurality of pogo pin receiving pad sets, each including a guard pad, occupy the periphery of the board. Each guard pad is electrically connected to a trace from the layer of conductive traces. The pad sets may be connected to the probing devices by low noise cables or traces. Air trenches separate the pad sets for reducing cross talk and signal settling times.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: November 23, 2004
    Assignee: Cascade Microtech, INC
    Inventors: Paul A. Tervo, Clarence E. Cowan
  • Patent number: 6801047
    Abstract: A wafer probe station is equipped with an integrated environment control enclosure substantially surrounding a supporting surface for holding a test device, such enclosure limiting fluid communication between the interior and exterior of the enclosure and preferably also providing EMI shielding and a dark environment. The limited communication between the interior and exterior of the enclosure is kept substantially constant despite positioning movement of either the supporting surface or probes. The positioning mechanisms for the supporting surface and probes each are located at least partially outside of the enclosure.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: October 5, 2004
    Assignee: Cascade Microtech, Inc.
    Inventors: Warren K. Harwood, Paul A. Tervo, Martin J. Koxxy
  • Publication number: 20040150416
    Abstract: To reduce noise in measurements obtained by probing a device supported on surface of a thermal chuck in a probe station, a conductive member is arranged to intercept current coupling the thermal unit of the chuck to the surface supporting the device. The conductive member is capacitively coupled to the thermal unit but free of direct electrical connection thereto.
    Type: Application
    Filed: July 25, 2003
    Publication date: August 5, 2004
    Inventors: Clarence E. Cowan, Paul A. Tervo, John L. Dunklee
  • Patent number: 6720782
    Abstract: A probe station includes a fully guarded chuck assembly and connector mechanism for increasing sensitivity to low-level currents while reducing settling times. The chuck assembly includes a wafer-supporting first chuck element surrounded by a second chuck element having a lower component, skirting component and upper component each with a surface portion extending opposite the first element for guarding thereof. The connector mechanism is so connected to the second chuck element as to enable, during low-level current measurements, the potential on each component to follow that on the first chuck element as measured relative to an outer shielding enclosure surrounding each element. Leakage current from the first chuck element is thus reduced to virtually zero, hence enabling increased current sensitivity, and the reduced capacitance thus provided by the second chuck element decreases charging periods, hence reducing settling times.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: April 13, 2004
    Assignee: Cascade Microtech, Inc.
    Inventors: Randy J. Schwindt, Warren K. Harwood, Paul A. Tervo, Kenneth R. Smith, Richard H. Warner